Lines Matching defs:ep_state
330 unsigned int ep_state;
335 ep_state = ep->ep_state;
336 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
337 && !(ep_state & EP_HALTED)) {
365 if (!(ep->ep_state & EP_HAS_STREAMS)) {
415 if (!(ep->ep_state & EP_HAS_STREAMS))
589 ep->ep_state |= SET_DEQ_PENDING;
595 ep->ep_state &= ~EP_HALT_PENDING;
794 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
898 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
906 unsigned int ep_state;
917 ep_state = ep_ctx->ep_info;
918 ep_state &= EP_STATE_MASK;
922 slot_state, ep_state);
945 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
977 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1020 unsigned int ep_state;
1074 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1075 if (!(ep_state & EP_HALTED))
1079 ep_index, ep_state);
1081 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1238 ep->ep_state |= EP_HALTED;
1774 ep->ep_state |= EP_HALTED;
2151 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2154 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2155 switch (ep_state) {