Lines Matching defs:xhci
23 #include "xhci.h"
29 void xhci_dbg_regs(struct xhci_hcd *xhci)
33 xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
34 xhci->cap_regs);
35 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
36 xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 &xhci->cap_regs->hc_capbase, temp);
38 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
41 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
43 temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
44 xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
45 &xhci->cap_regs->run_regs_off,
47 xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
49 temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
50 xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
51 xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
54 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
58 xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
60 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
61 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
63 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
65 xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
68 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
69 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
71 xhci_dbg(xhci, " Max device slots: %u\n",
73 xhci_dbg(xhci, " Max interrupters: %u\n",
75 xhci_dbg(xhci, " Max ports: %u\n",
78 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
79 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
81 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
83 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
86 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
87 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
89 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
91 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
94 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
95 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
96 xhci_dbg(xhci, " HC generates %s bit addresses\n",
98 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
100 temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
101 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
104 static void xhci_print_command_reg(struct xhci_hcd *xhci)
108 temp = xhci_readl(xhci, &xhci->op_regs->command);
109 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
110 xhci_dbg(xhci, " HC is %s\n",
112 xhci_dbg(xhci, " HC has %sfinished hard reset\n",
114 xhci_dbg(xhci, " Event Interrupts %s\n",
116 xhci_dbg(xhci, " Host System Error Interrupts %s\n",
118 xhci_dbg(xhci, " HC has %sfinished light reset\n",
122 static void xhci_print_status(struct xhci_hcd *xhci)
126 temp = xhci_readl(xhci, &xhci->op_regs->status);
127 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
128 xhci_dbg(xhci, " Event ring is %sempty\n",
130 xhci_dbg(xhci, " %sHost System Error\n",
132 xhci_dbg(xhci, " HC is %s\n",
136 static void xhci_print_op_regs(struct xhci_hcd *xhci)
138 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
139 xhci_print_command_reg(xhci);
140 xhci_print_status(xhci);
143 static void xhci_print_ports(struct xhci_hcd *xhci)
155 ports = HCS_MAX_PORTS(xhci->hcs_params1);
156 addr = &xhci->op_regs->port_status_base;
159 xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
161 (unsigned int) xhci_readl(xhci, addr));
167 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num)
174 temp = xhci_readl(xhci, addr);
178 xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
180 xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
184 temp = xhci_readl(xhci, addr);
185 xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
189 temp = xhci_readl(xhci, addr);
190 xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
194 temp = xhci_readl(xhci, addr);
196 xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
200 temp_64 = xhci_read_64(xhci, addr);
201 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
205 temp_64 = xhci_read_64(xhci, addr);
206 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
210 void xhci_print_run_regs(struct xhci_hcd *xhci)
215 xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
216 temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
217 xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
218 &xhci->run_regs->microframe_index,
221 temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
223 xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
224 &xhci->run_regs->rsvd[i],
229 void xhci_print_registers(struct xhci_hcd *xhci)
231 xhci_print_cap_regs(xhci);
232 xhci_print_op_regs(xhci);
233 xhci_print_ports(xhci);
236 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
240 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
247 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
250 u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
254 xhci_dbg(xhci, "Link TRB:\n");
255 xhci_print_trb_offsets(xhci, trb);
258 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
260 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
262 xhci_dbg(xhci, "Cycle bit = %u\n",
264 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
266 xhci_dbg(xhci, "No Snoop bit = %u\n",
271 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
275 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
276 xhci_dbg(xhci, "Completion status = %u\n",
278 xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
281 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
283 xhci_print_trb_offsets(xhci, trb);
288 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
296 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
305 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
307 xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
311 xhci_dbg(xhci, "Ring deq updated %u times\n",
313 xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
317 xhci_dbg(xhci, "Ring enq updated %u times\n",
330 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
334 xhci_debug_segment(xhci, first_seg);
337 xhci_dbg(xhci, " Ring has not been updated\n");
341 xhci_debug_segment(xhci, seg);
344 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
354 xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
356 xhci_debug_segment(xhci, ring->deq_seg);
362 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
364 xhci_debug_segment(xhci, ring->deq_seg);
368 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
376 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
386 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
390 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
391 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
393 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
398 static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
402 xhci_dbg(xhci, "@%p (virt) @%08llx "
410 char *xhci_get_slot_state(struct xhci_hcd *xhci,
413 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
429 void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
435 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
438 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
440 xhci_dbg(xhci, "Slot Context:\n");
441 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
445 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
449 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
453 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
458 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
465 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
468 void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
476 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
481 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
485 xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
486 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
490 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
494 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
498 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
503 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
511 dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
515 void xhci_dbg_ctx(struct xhci_hcd *xhci,
524 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
528 xhci_get_input_control_ctx(xhci, ctx);
529 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
533 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
538 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
545 dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
548 slot_ctx = xhci_get_slot_ctx(xhci, ctx);
549 xhci_dbg_slot_ctx(xhci, ctx);
550 xhci_dbg_ep_ctx(xhci, ctx, last_ep);