Lines Matching defs:imx21
61 #include "imx21-hcd.h"
64 #define DEBUG_LOG_FRAME(imx21, etd, event) \
65 (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
67 #define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
70 static const char hcd_name[] = "imx21-hcd";
72 static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
74 return (struct imx21 *)hcd->hcd_priv;
82 static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
84 void __iomem *reg = imx21->regs + offset;
88 static inline void clear_register_bits(struct imx21 *imx21,
91 void __iomem *reg = imx21->regs + offset;
95 static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
97 void __iomem *reg = imx21->regs + offset;
103 static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
105 void __iomem *reg = imx21->regs + offset;
111 static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
113 writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
116 static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
118 return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
134 struct imx21 *imx21 = hcd_to_imx21(hcd);
136 return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
140 #include "imx21-dbg.c"
146 static int alloc_etd(struct imx21 *imx21)
149 struct etd_priv *etd = imx21->etd;
153 memset(etd, 0, sizeof(imx21->etd[0]));
155 debug_etd_allocated(imx21);
162 static void disactivate_etd(struct imx21 *imx21, int num)
165 struct etd_priv *etd = &imx21->etd[num];
167 writel(etd_mask, imx21->regs + USBH_ETDENCLR);
168 clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
169 writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
170 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
174 DEBUG_LOG_FRAME(imx21, etd, disactivated);
177 static void reset_etd(struct imx21 *imx21, int num)
179 struct etd_priv *etd = imx21->etd + num;
182 disactivate_etd(imx21, num);
185 etd_writel(imx21, num, i, 0);
191 static void free_etd(struct imx21 *imx21, int num)
197 dev_err(imx21->dev, "BAD etd=%d!\n", num);
200 if (imx21->etd[num].alloc == 0) {
201 dev_err(imx21->dev, "ETD %d already free!\n", num);
205 debug_etd_freed(imx21);
206 reset_etd(imx21, num);
207 memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
211 static void setup_etd_dword0(struct imx21 *imx21,
214 etd_writel(imx21, etd_num, 0,
224 static void activate_etd(struct imx21 *imx21,
228 struct etd_priv *etd = &imx21->etd[etd_num];
230 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
231 set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
232 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
233 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
236 set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
237 clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
238 clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
239 writel(dma, imx21->regs + USB_ETDSMSA(etd_num));
240 set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
244 set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
245 set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
249 DEBUG_LOG_FRAME(imx21, etd, activated);
254 etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
260 etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
265 writel(etd_mask, imx21->regs + USBH_ETDENSET);
272 static int alloc_dmem(struct imx21 *imx21, unsigned int size,
282 dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
287 list_for_each_entry(tmp, &imx21->dmem_list, list) {
305 debug_dmem_allocated(imx21, size);
313 static void activate_queued_etd(struct imx21 *imx21,
317 int etd_num = etd - &imx21->etd[0];
318 u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
319 u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
321 dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
323 etd_writel(imx21, etd_num, 1,
327 activate_etd(imx21, etd_num, etd->dma_handle, dir);
330 static void free_dmem(struct imx21 *imx21, int offset)
336 list_for_each_entry(area, &imx21->dmem_list, list) {
338 debug_dmem_freed(imx21, area->size);
347 dev_err(imx21->dev,
353 list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
354 offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
357 activate_queued_etd(imx21, etd, (u32)offset);
362 static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
366 list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
368 dev_err(imx21->dev,
381 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
384 static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
395 if (list_empty(&imx21->queue_for_etd)) {
396 free_etd(imx21, etd_num);
400 dev_dbg(imx21->dev,
402 ep_priv = list_first_entry(&imx21->queue_for_etd,
405 reset_etd(imx21, etd_num);
410 dev_err(imx21->dev, "No urb for queued ep!\n");
413 schedule_nonisoc_etd(imx21, list_first_entry(
419 __releases(imx21->lock)
420 __acquires(imx21->lock)
422 struct imx21 *imx21 = hcd_to_imx21(hcd);
426 debug_urb_completed(imx21, urb, status);
427 dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
433 spin_unlock(&imx21->lock);
435 spin_lock(&imx21->lock);
437 ep_idle(imx21, ep_priv);
447 struct imx21 *imx21 = hcd_to_imx21(hcd);
466 etd = &imx21->etd[etd_num];
476 dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
493 debug_isoc_submitted(imx21, cur_frame, td);
496 setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
497 etd_writel(imx21, etd_num, 1, etd->dmem_offset);
498 etd_writel(imx21, etd_num, 2,
501 etd_writel(imx21, etd_num, 3,
505 activate_etd(imx21, etd_num, td->data, dir);
511 struct imx21 *imx21 = hcd_to_imx21(hcd);
514 struct etd_priv *etd = imx21->etd + etd_num;
523 disactivate_etd(imx21, etd_num);
525 cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
526 bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
537 debug_isoc_completed(imx21,
541 dev_dbg(imx21->dev,
549 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
566 struct imx21 *imx21, struct usb_host_endpoint *ep)
577 ep_priv->etd[i] = alloc_etd(imx21);
580 dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
582 free_etd(imx21, ep_priv->etd[j]);
585 imx21->etd[ep_priv->etd[i]].ep = ep;
602 struct imx21 *imx21 = hcd_to_imx21(hcd);
623 spin_lock_irqsave(&imx21->lock, flags);
626 ep_priv = alloc_isoc_ep(imx21, ep);
648 struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
652 dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
659 etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
661 dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
681 dev_dbg(imx21->dev,
701 dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
704 debug_urb_submitted(imx21, urb);
707 spin_unlock_irqrestore(&imx21->lock, flags);
715 spin_unlock_irqrestore(&imx21->lock, flags);
723 static void dequeue_isoc_urb(struct imx21 *imx21,
733 if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
734 struct etd_priv *etd = imx21->etd + etd_num;
736 reset_etd(imx21, etd_num);
738 free_dmem(imx21, etd->dmem_offset);
746 dev_vdbg(imx21->dev, "removing td %p\n", td);
756 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
775 dev_err(imx21->dev, "No valid ETD\n");
778 if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
779 dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
781 etd = &imx21->etd[etd_num];
828 relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
832 setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
834 etd_writel(imx21, etd_num, 2,
850 etd_writel(imx21, etd_num, 3,
858 dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
861 etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
863 dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
864 debug_urb_queued_for_dmem(imx21, urb);
865 list_add_tail(&etd->queue, &imx21->queue_for_dmem);
869 etd_writel(imx21, etd_num, 1,
876 dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
878 activate_etd(imx21, etd_num, etd->dma_handle, dir);
884 struct imx21 *imx21 = hcd_to_imx21(hcd);
885 struct etd_priv *etd = &imx21->etd[etd_num];
894 disactivate_etd(imx21, etd_num);
896 dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
897 xbufaddr = etd_readl(imx21, etd_num, 1) & 0xffff;
898 cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
899 bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
904 (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
907 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
908 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
910 free_dmem(imx21, xbufaddr);
918 dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
939 dev_err(imx21->dev,
968 dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
969 schedule_nonisoc_etd(imx21, urb);
979 dev_vdbg(imx21->dev, "next URB %p\n", urb);
980 schedule_nonisoc_etd(imx21, urb);
1003 struct imx21 *imx21 = hcd_to_imx21(hcd);
1012 dev_vdbg(imx21->dev,
1027 spin_lock_irqsave(&imx21->lock, flags);
1060 debug_urb_submitted(imx21, urb);
1063 dev_dbg(imx21->dev,
1066 debug_urb_queued_for_etd(imx21, urb);
1069 ep_priv->etd[0] = alloc_etd(imx21);
1071 dev_dbg(imx21->dev,
1073 debug_urb_queued_for_etd(imx21, urb);
1074 list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
1081 etd = &imx21->etd[ep_priv->etd[0]];
1083 DEBUG_LOG_FRAME(imx21, etd, last_req);
1084 schedule_nonisoc_etd(imx21, urb);
1088 spin_unlock_irqrestore(&imx21->lock, flags);
1093 spin_unlock_irqrestore(&imx21->lock, flags);
1101 struct imx21 *imx21 = hcd_to_imx21(hcd);
1108 dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
1111 spin_lock_irqsave(&imx21->lock, flags);
1119 debug_urb_unlinked(imx21, urb);
1122 dequeue_isoc_urb(imx21, urb, ep_priv);
1127 disactivate_etd(imx21, etd_num);
1128 free_dmem(imx21, etd_readl(imx21, etd_num, 1) & 0xffff);
1129 imx21->etd[etd_num].urb = NULL;
1135 spin_unlock_irqrestore(&imx21->lock, flags);
1139 spin_unlock_irqrestore(&imx21->lock, flags);
1147 static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
1153 spin_lock_irqsave(&imx21->lock, flags);
1157 u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
1158 u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
1159 struct etd_priv *etd = &imx21->etd[etd_num];
1163 DEBUG_LOG_FRAME(imx21, etd, last_int);
1190 cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
1197 dword0 = etd_readl(imx21, etd_num, 0);
1198 dev_dbg(imx21->dev,
1205 dev_dbg(imx21->dev,
1212 readl(imx21->regs + USBH_FRMNUB));
1213 imx21->debug_unblocks++;
1220 dev_dbg(imx21->dev,
1224 disactivate_etd(imx21, etd_num);
1236 set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1238 clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1241 spin_unlock_irqrestore(&imx21->lock, flags);
1246 struct imx21 *imx21 = hcd_to_imx21(hcd);
1247 u32 ints = readl(imx21->regs + USBH_SYSISR);
1250 dev_dbg(imx21->dev, "Scheduling error\n");
1253 dev_dbg(imx21->dev, "Scheduling overrun\n");
1256 process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
1258 writel(ints, imx21->regs + USBH_SYSISR);
1265 struct imx21 *imx21 = hcd_to_imx21(hcd);
1273 spin_lock_irqsave(&imx21->lock, flags);
1275 dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
1278 dev_dbg(imx21->dev, "ep's URB list is not empty\n");
1283 dev_dbg(imx21->dev, "free etd %d for disable\n",
1286 free_etd(imx21, ep_priv->etd[i]);
1293 if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
1294 dev_err(imx21->dev,
1296 free_etd(imx21, i);
1299 free_epdmem(imx21, ep);
1300 spin_unlock_irqrestore(&imx21->lock, flags);
1310 struct imx21 *imx21 = hcd_to_imx21(hcd);
1314 desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
1330 struct imx21 *imx21 = hcd_to_imx21(hcd);
1336 spin_lock_irqsave(&imx21->lock, flags);
1337 ports = readl(imx21->regs + USBH_ROOTHUBA)
1341 dev_err(imx21->dev, "ports %d > 7\n", ports);
1344 if (readl(imx21->regs + USBH_PORTSTAT(i)) &
1355 spin_unlock_irqrestore(&imx21->lock, flags);
1358 dev_info(imx21->dev, "Hub status changed\n");
1366 struct imx21 *imx21 = hcd_to_imx21(hcd);
1372 dev_dbg(imx21->dev, "ClearHubFeature\n");
1375 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1378 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1381 dev_dbg(imx21->dev, " unknown\n");
1388 dev_dbg(imx21->dev, "ClearPortFeature\n");
1391 dev_dbg(imx21->dev, " ENABLE\n");
1395 dev_dbg(imx21->dev, " SUSPEND\n");
1399 dev_dbg(imx21->dev, " POWER\n");
1403 dev_dbg(imx21->dev, " C_ENABLE\n");
1407 dev_dbg(imx21->dev, " C_SUSPEND\n");
1411 dev_dbg(imx21->dev, " C_CONNECTION\n");
1415 dev_dbg(imx21->dev, " C_OVER_CURRENT\n");
1419 dev_dbg(imx21->dev, " C_RESET\n");
1423 dev_dbg(imx21->dev, " unknown\n");
1431 dev_dbg(imx21->dev, "GetHubDescriptor\n");
1436 dev_dbg(imx21->dev, " GetHubStatus\n");
1441 dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
1443 *(__le32 *) buf = readl(imx21->regs +
1448 dev_dbg(imx21->dev, "SetHubFeature\n");
1451 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1455 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1458 dev_dbg(imx21->dev, " unknown\n");
1466 dev_dbg(imx21->dev, "SetPortFeature\n");
1469 dev_dbg(imx21->dev, " SUSPEND\n");
1473 dev_dbg(imx21->dev, " POWER\n");
1477 dev_dbg(imx21->dev, " RESET\n");
1481 dev_dbg(imx21->dev, " unknown\n");
1488 dev_dbg(imx21->dev, " unknown\n");
1494 writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
1504 struct imx21 *imx21 = hcd_to_imx21(hcd);
1508 spin_lock_irqsave(&imx21->lock, flags);
1513 imx21->regs + USBOTG_RST_CTRL);
1517 while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
1519 spin_unlock_irqrestore(&imx21->lock, flags);
1520 dev_err(imx21->dev, "timeout waiting for reset\n");
1523 spin_unlock_irq(&imx21->lock);
1525 spin_lock_irq(&imx21->lock);
1527 spin_unlock_irqrestore(&imx21->lock, flags);
1533 struct imx21 *imx21 = hcd_to_imx21(hcd);
1539 hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
1541 hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
1544 if (imx21->pdata->host1_txenoe)
1547 if (!imx21->pdata->host1_xcverless)
1550 if (imx21->pdata->otg_ext_xcvr)
1554 spin_lock_irqsave(&imx21->lock, flags);
1557 imx21->regs + USBOTG_CLK_CTRL);
1558 writel(hw_mode, imx21->regs + USBOTG_HWMODE);
1559 writel(usb_control, imx21->regs + USBCTRL);
1561 imx21->regs + USB_MISCCONTROL);
1566 etd_writel(imx21, i, j, 0);
1570 imx21->regs + USBH_HOST_CTRL);
1573 if (imx21->pdata->enable_otg_host)
1575 imx21->regs + USBH_PORTSTAT(0));
1577 if (imx21->pdata->enable_host1)
1579 imx21->regs + USBH_PORTSTAT(1));
1581 if (imx21->pdata->enable_host2)
1583 imx21->regs + USBH_PORTSTAT(2));
1589 set_register_bits(imx21, USBH_SYSIEN,
1592 set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1594 spin_unlock_irqrestore(&imx21->lock, flags);
1601 struct imx21 *imx21 = hcd_to_imx21(hcd);
1604 spin_lock_irqsave(&imx21->lock, flags);
1606 writel(0, imx21->regs + USBH_SYSIEN);
1607 clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1608 clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
1610 spin_unlock_irqrestore(&imx21->lock, flags);
1620 .hcd_priv_size = sizeof(struct imx21),
1655 struct imx21 *imx21 = hcd_to_imx21(hcd);
1658 remove_debug_files(imx21);
1662 clk_disable(imx21->clk);
1663 clk_put(imx21->clk);
1664 iounmap(imx21->regs);
1676 struct imx21 *imx21;
1698 imx21 = hcd_to_imx21(hcd);
1699 imx21->dev = &pdev->dev;
1700 imx21->pdata = pdev->dev.platform_data;
1701 if (!imx21->pdata)
1702 imx21->pdata = &default_pdata;
1704 spin_lock_init(&imx21->lock);
1705 INIT_LIST_HEAD(&imx21->dmem_list);
1706 INIT_LIST_HEAD(&imx21->queue_for_etd);
1707 INIT_LIST_HEAD(&imx21->queue_for_dmem);
1708 create_debug_files(imx21);
1716 imx21->regs = ioremap(res->start, resource_size(res));
1717 if (imx21->regs == NULL) {
1718 dev_err(imx21->dev, "Cannot map registers\n");
1724 imx21->clk = clk_get(imx21->dev, NULL);
1725 if (IS_ERR(imx21->clk)) {
1726 dev_err(imx21->dev, "no clock found\n");
1727 ret = PTR_ERR(imx21->clk);
1731 ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
1734 ret = clk_enable(imx21->clk);
1738 dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
1739 (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
1743 dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
1750 clk_disable(imx21->clk);
1753 clk_put(imx21->clk);
1755 iounmap(imx21->regs);
1759 remove_debug_files(imx21);
1790 MODULE_ALIAS("platform:imx21-hcd");