Lines Matching refs:ehci_readl
65 status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
95 status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
134 temp = ehci_readl(ehci, hostpc_reg);
145 u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
170 temp = ehci_readl(ehci, hostpc_reg);
176 if (!suspending && (ehci_readl(ehci, &ehci->regs->status) & STS_PCD))
221 ehci->command = ehci_readl(ehci, &ehci->regs->command);
235 u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
279 t3 = ehci_readl(ehci, hostpc_reg);
281 t3 = ehci_readl(ehci, hostpc_reg);
304 ehci_readl(ehci, &ehci->regs->intr_enable);
347 power_okay = ehci_readl(ehci, &ehci->regs->intr_enable);
379 temp = ehci_readl(ehci, hostpc_reg);
392 temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
411 temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
419 (void) ehci_readl(ehci, &ehci->regs->command);
493 port_status = ehci_readl(ehci, status_reg);
649 ppcd = ehci_readl(ehci, &ehci->regs->status) >> 16;
655 temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
748 temp = ehci_readl(ehci, status_reg);
777 temp1 = ehci_readl(ehci, hostpc_reg);
818 ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
834 temp = ehci_readl(ehci, status_reg);
880 temp = ehci_readl(ehci, status_reg);
919 ehci_readl(ehci, status_reg));
932 temp = ehci_readl(ehci, status_reg);
945 temp1 = ehci_readl(ehci, hostpc_reg);
1003 temp = ehci_readl(ehci, status_reg);
1027 temp1 = ehci_readl(ehci, hostpc_reg);
1030 temp1 = ehci_readl(ehci, hostpc_reg);
1089 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1119 return ehci_readl(ehci, reg) & PORT_OWNER;