Lines Matching refs:ep0state
388 dev->ep0state = EP0_IDLE;
700 switch (dev->ep0state) {
717 dev->ep0state = EP0_END_XFER;
732 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
847 ep->dev->ep0state = EP0_STALL;
1200 dev->ep0state = EP0_IDLE;
1456 if (dev->ep0state == EP0_STALL
1491 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1497 switch (dev->ep0state) {
1573 dev->ep0state = EP0_IN_DATA_PHASE;
1575 dev->ep0state = EP0_OUT_DATA_PHASE;
1602 dev->ep0state = EP0_STALL;
1606 if (likely(dev->ep0state == EP0_IN_DATA_PHASE