Lines Matching defs:pipenum
62 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
70 m66592_bset(m66592, (1 << pipenum), reg);
74 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
82 m66592_bclr(m66592, (1 << pipenum), reg);
115 static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
120 if (pipenum == 0)
122 else if (pipenum < M66592_MAX_NUM_PIPE) {
123 offset = get_pipectr_addr(pipenum);
126 pr_err("unexpect pipe num (%d)\n", pipenum);
131 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
136 if (pipenum == 0)
138 else if (pipenum < M66592_MAX_NUM_PIPE) {
139 offset = get_pipectr_addr(pipenum);
142 pr_err("unexpect pipe num (%d)\n", pipenum);
145 static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
147 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
150 static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
152 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
155 static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
157 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
160 static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
165 if (pipenum == 0)
167 else if (pipenum < M66592_MAX_NUM_PIPE) {
168 offset = get_pipectr_addr(pipenum);
171 pr_err("unexpect pipe num (%d)\n", pipenum);
176 static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
180 pipe_stop(m66592, pipenum);
182 if (pipenum == 0)
184 else if (pipenum < M66592_MAX_NUM_PIPE) {
185 offset = get_pipectr_addr(pipenum);
188 pr_err("unexpect pipe num(%d)\n", pipenum);
191 static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
196 if (pipenum == 0) {
205 m66592_write(m66592, pipenum, M66592_PIPESEL);
219 static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
221 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
227 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
309 pr_err("ep_release: unexpect pipenum (%d)\n",
324 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
339 u16 pipenum, int dma)
341 if ((pipenum != 0) && dma) {
371 ep->pipectr = get_pipectr_addr(pipenum);
372 ep->pipenum = pipenum;
374 m66592->pipenum2ep[pipenum] = ep;
382 u16 pipenum = ep->pipenum;
384 if (pipenum == 0)
389 ep->pipenum = 0;
405 BUG_ON(ep->pipenum);
478 info.pipe = ep->pipenum;
487 static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
489 enable_irq_ready(m66592, pipenum);
490 enable_irq_nrdy(m66592, pipenum);
493 static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
495 disable_irq_ready(m66592, pipenum);
496 disable_irq_nrdy(m66592, pipenum);
511 pipe_change(m66592, ep->pipenum);
531 pipe_change(m66592, ep->pipenum);
532 disable_irq_empty(m66592, ep->pipenum);
533 pipe_start(m66592, ep->pipenum);
537 pipe_irq_enable(m66592, ep->pipenum);
545 u16 pipenum = ep->pipenum;
547 if (ep->pipenum == 0) {
552 pipe_start(m66592, pipenum);
553 pipe_irq_enable(m66592, pipenum);
557 pipe_change(m66592, pipenum);
564 pipe_start(m66592, pipenum); /* trigger once */
565 pipe_irq_enable(m66592, pipenum);
724 if (unlikely(ep->pipenum == 0)) {
758 u16 pipenum = ep->pipenum;
761 pipe_change(m66592, pipenum);
776 bufsize = get_buffer_size(m66592, pipenum);
795 disable_irq_ready(m66592, pipenum);
796 disable_irq_empty(m66592, pipenum);
798 disable_irq_ready(m66592, pipenum);
799 enable_irq_empty(m66592, pipenum);
801 pipe_start(m66592, pipenum);
810 u16 pipenum = ep->pipenum;
813 pipe_change(m66592, pipenum);
816 pipe_stop(m66592, pipenum);
817 pipe_irq_disable(m66592, pipenum);
818 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
823 bufsize = get_buffer_size(m66592, pipenum);
843 disable_irq_ready(m66592, pipenum);
844 enable_irq_empty(m66592, pipenum);
846 disable_irq_empty(m66592, pipenum);
847 pipe_irq_enable(m66592, pipenum);
857 u16 pipenum = ep->pipenum;
861 pipe_change(m66592, pipenum);
865 pipe_stop(m66592, pipenum);
866 pipe_irq_disable(m66592, pipenum);
873 bufsize = get_buffer_size(m66592, pipenum);
889 pipe_stop(m66592, pipenum);
890 pipe_irq_disable(m66592, pipenum);
902 if ((ep->pipenum != 0) && finish)
909 u16 pipenum;
922 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
923 check = 1 << pipenum;
926 ep = m66592->pipenum2ep[pipenum];
942 u16 pipenum;
953 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
954 check = 1 << pipenum;
957 tmp = control_reg_get(m66592, pipenum);
959 disable_irq_empty(m66592, pipenum);
960 pipe_irq_disable(m66592, pipenum);
961 pipe_stop(m66592, pipenum);
962 ep = m66592->pipenum2ep[pipenum];
992 pid = control_reg_get_pid(m66592, ep->pipenum);
1027 pipe_stop(m66592, ep->pipenum);
1028 control_reg_sqclr(m66592, ep->pipenum);
1040 pipe_start(m66592, ep->pipenum);
1064 pipe_stall(m66592, ep->pipenum);
1320 pipe_irq_disable(ep->m66592, ep->pipenum);
1415 pipe_stall(ep->m66592, ep->pipenum);
1418 pipe_stop(ep->m66592, ep->pipenum);
1434 pipe_stop(ep->m66592, ep->pipenum);
1675 m66592->ep[0].pipenum = 0;