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  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/xgifb/

Lines Matching defs:pVBInfo

83 				     struct vb_device_info *pVBInfo);
98 void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
99 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
102 void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
103 void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
104 void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
105 unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo);
106 void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
107 unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo);
125 struct vb_device_info *pVBInfo = &VBINF;
136 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
138 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
140 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
142 pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
148 /* if ( pVBInfo->ROMAddr == 0 ) */
151 if (pVBInfo->FBAddr == 0) {
152 printk("\n pVBInfo->FBAddr == 0 ");
156 if (pVBInfo->BaseAddr == 0) {
162 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
164 pVBInfo->ISXPDOS = 0 ;
176 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
177 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
178 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
179 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
180 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
181 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
182 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
183 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
184 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
185 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
186 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
187 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
188 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
189 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
190 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
191 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
192 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
196 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
198 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
201 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
204 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
210 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
214 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
221 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
224 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
227 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
234 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
239 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
244 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
247 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
250 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
255 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
260 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
263 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
268 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
271 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
272 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
274 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
275 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
276 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
277 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
278 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
283 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
290 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
304 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
313 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
315 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
318 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
328 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
331 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
334 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
340 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
347 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
352 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
356 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
357 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
358 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
364 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
365 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
366 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
367 temp1 = (unsigned char)XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
371 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
375 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
379 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
381 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
383 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
384 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
388 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
389 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
391 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
396 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
400 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
402 if ( pVBInfo->IF_DEF_LVDS == 0 )
404 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
405 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
406 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
407 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
408 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
411 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
417 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
423 XGI_SenseCRT1(pVBInfo) ;
427 pVBInfo->IF_DEF_CH7007 = 0;
428 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
431 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
439 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
440 temp = GetXG21FPBits( pVBInfo ) ;
441 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
447 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
448 temp = GetXG27FPBits( pVBInfo ) ;
449 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
458 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
461 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
469 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
473 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
480 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
493 temp =(unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x3A) ;
499 *pVBInfo->pSR21 &= 0xEF ;
501 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
503 *pVBInfo->pSR22 &= 0x20 ;
504 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
512 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char)((*pVBInfo->pSR22) & 0xFE));
516 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
519 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
524 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
525 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
530 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
531 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
550 struct vb_device_info *pVBInfo)
556 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
558 data = *pVBInfo->pSoftSetting & 0x07 ;
563 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
566 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
573 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
575 data = *pVBInfo->pSoftSetting & 0x07 ;
578 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
588 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
590 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
591 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
599 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
604 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
620 unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo)
624 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
627 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
628 data = *pVBInfo->pSoftSetting & 0x03 ;
630 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
656 void XGINew_SDR_MRS(struct vb_device_info *pVBInfo)
660 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
662 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
665 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
676 void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
683 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
693 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
695 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
696 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
700 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
702 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
703 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
714 void XGINew_DDR2x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
721 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
730 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
744 unsigned long P3c4, struct vb_device_info *pVBInfo)
747 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
748 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
752 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
823 unsigned long P3c4, struct vb_device_info *pVBInfo)
827 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
828 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
876 unsigned long P3c4, struct vb_device_info *pVBInfo)
880 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
881 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
955 unsigned long Port, struct vb_device_info *pVBInfo)
962 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
963 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
964 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
965 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
970 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
974 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
980 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
981 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
982 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
990 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
996 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
997 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1004 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1016 unsigned long Port, struct vb_device_info *pVBInfo)
1021 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1028 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1029 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1030 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1043 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1044 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1057 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1068 unsigned long Port, struct vb_device_info *pVBInfo)
1079 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1085 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1087 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1094 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1096 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1107 unsigned long Port, struct vb_device_info *pVBInfo)
1115 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1116 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1117 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1118 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1123 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1138 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1157 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1171 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1172 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1175 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1186 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1191 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1198 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1201 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1204 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1207 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1210 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1215 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1219 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1232 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1234 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1238 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1240 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1250 void XGINew_DDR_MRS(struct vb_device_info *pVBInfo)
1254 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
1260 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1263 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1265 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1267 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1269 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1271 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1273 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1275 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1277 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1282 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1284 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1290 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1295 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1296 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1302 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1318 void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1320 unsigned char *pVideoMemory = pVBInfo->FBAddr ;
1331 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1333 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1335 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1339 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1342 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1364 void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1368 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1369 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1374 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1375 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1376 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1378 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1380 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1381 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1382 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1383 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1393 void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1396 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1397 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1399 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1403 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1404 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1405 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1410 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1411 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1413 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1415 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1417 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1420 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short)(data | 0x0F)); /* assume lowest speed DRAM */
1422 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1423 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1424 XGINew_CheckBusWidth_310( pVBInfo) ;
1425 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1429 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1431 XGINew_SDRSizing( pVBInfo ) ;
1435 XGINew_DDRSizing( pVBInfo) ;
1441 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
1443 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1444 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1445 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1461 struct vb_device_info *pVBInfo = &VBINF;
1462 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1463 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1464 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
1465 pVBInfo->ISXPDOS = 0 ;
1467 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1468 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1469 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1470 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1471 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1472 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1473 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1474 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1475 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1476 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1477 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1478 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1479 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1480 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1481 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1482 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1483 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1485 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1487 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1489 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1491 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1493 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1495 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1497 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1500 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1502 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1511 void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo)
1513 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1515 XGINew_SDR_MRS(pVBInfo ) ;
1520 XGINew_DDR_MRS( pVBInfo ) ;
1531 void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1536 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1538 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1549 void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1552 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1566 struct vb_device_info *pVBInfo)
1570 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1590 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1602 struct vb_device_info *pVBInfo)
1607 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1619 void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo)
1624 pVideoMemory = (unsigned long *) pVBInfo->FBAddr;
1626 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1628 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1629 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1631 XGINew_SDR_MRS( pVBInfo ) ;
1649 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1650 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (unsigned short)(data & 0xFD));
1658 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1659 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1668 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1669 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1671 XGINew_DDR_MRS( pVBInfo ) ;
1698 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1703 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1704 XGINew_DDR_MRS( pVBInfo);
1736 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1757 struct vb_device_info *pVBInfo)
1778 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1780 XGINew_SDR_MRS( pVBInfo ) ;
1798 struct vb_device_info *pVBInfo)
1818 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1820 XGINew_DDR_MRS( pVBInfo ) ;
1836 struct vb_device_info *pVBInfo)
1846 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1853 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1854 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1870 struct vb_device_info *pVBInfo)
1879 /* pVBInfo->FBAddr[ Position ] = Position ; */
1880 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1886 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1887 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1903 struct vb_device_info *pVBInfo)
1913 /* pVBInfo->FBAddr[ Position ] = Position ; */
1914 /* *( (unsigned long *)( pVBInfo->FBAddr ) ) = Position ; */
1915 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1921 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1922 /* if ( ( *(unsigned long *)( pVBInfo->FBAddr ) ) != Position ) */
1923 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1939 struct vb_device_info *pVBInfo)
1950 *((unsigned long *)(pVBInfo->FBAddr + Position + 0)) = 0x01234567;
1951 *((unsigned long *)(pVBInfo->FBAddr + Position + 1)) = 0x456789AB;
1952 *((unsigned long *)(pVBInfo->FBAddr + Position + 2)) = 0x55555555;
1953 *((unsigned long *)(pVBInfo->FBAddr + Position + 3)) = 0x55555555;
1954 *((unsigned long *)(pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA;
1955 *((unsigned long *)(pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA;
1957 if ((*(unsigned long *)(pVBInfo->FBAddr + 1)) == 0x456789AB)
1960 if ((*(unsigned long *)(pVBInfo->FBAddr + 0)) == 0x01234567)
1963 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1966 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1967 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1969 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1983 struct vb_device_info *pVBInfo)
1989 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
1993 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
1996 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2011 struct vb_device_info *pVBInfo)
2017 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2021 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2024 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2037 int XGINew_SDRSizing(struct vb_device_info *pVBInfo)
2044 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2049 XGINew_SDRDRAM_TYPE, pVBInfo))
2053 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2070 struct vb_device_info *pVBInfo)
2077 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2100 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2104 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2107 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2121 struct vb_device_info *pVBInfo)
2128 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2151 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2156 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2159 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2172 struct vb_device_info *pVBInfo)
2177 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
2182 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
2189 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2195 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2208 unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
2212 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2216 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2231 void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2239 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2250 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2251 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2254 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2259 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2260 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2263 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2271 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2272 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2275 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2289 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2293 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2298 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2299 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2302 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2311 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2312 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2315 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2330 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2335 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2337 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2341 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2343 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2348 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2352 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2355 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2358 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2360 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2363 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2370 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2372 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2376 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2378 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2381 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2383 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2387 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2390 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2394 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2396 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2399 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2412 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2416 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2419 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2422 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2423 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2424 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2428 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2429 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2431 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2443 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2446 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2450 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2459 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2464 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2466 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2472 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2475 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2476 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2478 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2490 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2493 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2497 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2498 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2512 int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2518 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2519 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2526 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2527 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2535 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2543 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2544 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2553 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2567 int XGINew_DDRSizing(struct vb_device_info *pVBInfo)
2574 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2575 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2578 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2580 XGINew_DDRDRAM_TYPE, pVBInfo))
2584 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2598 void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2602 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2603 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2604 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2608 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2609 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2610 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2616 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2617 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2618 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2619 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
2630 unsigned char ChkLFB(struct vb_device_info *pVBInfo)
2632 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4 , 0x78))
2676 void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2680 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2681 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2682 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2683 pVBInfo->ISXPDOS = 0 ;
2685 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2686 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2687 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2688 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2689 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2690 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2691 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2692 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2693 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2694 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2695 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2696 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2697 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2698 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2699 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2700 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2701 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2703 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2713 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2725 void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
2727 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
2734 pVBInfo->IF_DEF_LVDS = 0 ;
2737 pVBInfo->IF_DEF_LVDS = 1 ;
2745 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2746 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2747 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2748 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2749 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2750 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2751 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2752 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2753 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2754 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2755 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2756 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2757 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2758 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2759 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2760 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2769 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2770 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2771 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2772 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2773 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2774 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2775 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2776 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2777 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2778 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2779 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2780 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2781 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2782 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2783 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2784 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2796 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
2810 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2819 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2835 struct vb_device_info *pVBInfo = &VBINF;
2836 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2837 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2838 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2839 pVBInfo->ISXPDOS = 0 ;
2841 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2842 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2843 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2844 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2845 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2846 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2847 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2848 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2849 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2850 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2851 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2852 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2853 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2854 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2855 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2856 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2857 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2859 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2861 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2863 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2864 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2866 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2868 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2874 struct vb_device_info *pVBInfo = &VBINF;
2875 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2876 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2877 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2878 pVBInfo->ISXPDOS = 0 ;
2880 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2881 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2882 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2883 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2884 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2885 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2886 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2887 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2888 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2889 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2890 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2891 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2892 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2893 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2894 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2895 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2896 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2898 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2900 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2902 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2903 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2905 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2906 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
2908 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2909 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
2918 struct vb_device_info *pVBInfo = &VBINF;
2919 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2920 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2921 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
2922 pVBInfo->ISXPDOS = 0 ;
2924 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2925 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2926 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2927 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2928 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2929 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2930 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2931 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2932 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2933 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2934 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2935 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2936 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2937 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2938 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2939 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2940 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2942 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2944 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2946 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2947 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2949 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2951 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2960 void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2964 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
2987 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
2988 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
2992 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
2996 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3005 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3012 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3013 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3021 void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3025 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3026 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3027 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3029 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3052 if ( pVBInfo->IF_DEF_HiVision == 1 )
3058 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3075 if ( pVBInfo->IF_DEF_HiVision == 1 )
3081 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3094 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3096 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3103 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3105 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3108 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3118 void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3121 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
3123 pVBInfo->IF_DEF_LVDS = 0 ;
3127 pVBInfo->IF_DEF_LVDS = 1 ;
3128 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3129 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3133 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3134 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3137 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3138 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3139 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3140 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3142 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3144 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3145 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3156 void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3160 pVBInfo->IF_DEF_LVDS = 0 ;
3161 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3162 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3163 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3164 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3168 pVBInfo->IF_DEF_LVDS = 1 ;
3169 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3170 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3174 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3176 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3180 unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
3184 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3185 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3186 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3190 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3195 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3200 unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
3204 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3205 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3206 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3215 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;