Lines Matching defs:P3d4
177 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
247 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
250 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
255 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
304 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
313 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
315 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
318 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
328 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
331 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
334 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
340 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
347 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
352 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
367 temp1 = (unsigned char)XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
417 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
439 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
441 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
447 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
449 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
461 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
530 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
588 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
590 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
591 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
599 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
604 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
746 unsigned long P3d4 = P3c4 + 0x10 ;
751 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
752 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
825 unsigned long P3d4 = P3c4 + 0x10 ;
830 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
878 unsigned long P3d4 = P3c4 + 0x10 ;
883 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
957 unsigned long P3d4 = Port ,
963 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
964 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
965 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
967 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
968 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
980 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
981 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
982 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
985 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
986 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
987 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
988 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
989 XGINew_GetReg1( P3d4 , 0x86 ) ;
990 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
991 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
992 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
993 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
994 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
995 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
996 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
997 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1001 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1002 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1003 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1018 unsigned long P3d4 = Port ,
1028 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1029 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1030 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1034 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1035 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1036 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1037 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1038 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1039 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1040 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1041 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1042 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1043 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1044 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1046 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1049 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1053 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1055 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1070 unsigned long P3d4 = Port ,
1074 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1075 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1076 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1077 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1078 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1079 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1080 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1081 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1082 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1083 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1084 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1085 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1087 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1089 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1091 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1092 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1112 unsigned long P3d4 = Port ,
1115 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1116 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1117 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1118 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1128 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1129 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1143 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1144 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1153 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1162 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1163 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1171 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1172 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1180 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1181 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1189 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1195 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1196 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1197 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1198 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1201 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1204 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1207 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1210 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1213 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1215 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1217 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1218 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1219 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1234 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1237 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1238 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1399 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1403 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1404 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1405 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1468 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2212 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2239 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2632 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4 , 0x78))
2686 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2842 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2881 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2925 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2964 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
2987 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
2988 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
2992 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3012 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3013 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3025 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3026 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3027 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3094 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3096 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3103 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3105 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3108 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3128 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3129 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3133 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3134 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3138 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3139 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3140 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3142 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3144 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3145 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3161 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3162 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3163 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3164 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3169 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3170 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3174 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3176 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3184 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3185 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3186 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3190 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3195 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3204 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3205 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3206 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3215 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;