Lines Matching defs:P3c4
99 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
176 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
204 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
221 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
224 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
227 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
234 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
239 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
244 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
268 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
271 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
272 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
274 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
275 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
276 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
277 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
278 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
283 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
290 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
356 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
357 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
358 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
379 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
383 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
384 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
388 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
389 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
391 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
396 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
469 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
493 temp =(unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x3A) ;
501 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
504 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
512 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char)((*pVBInfo->pSR22) & 0xFE));
516 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
519 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
531 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
563 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
566 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
578 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
624 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
630 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
660 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
662 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
665 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
676 void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
678 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
679 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
680 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
681 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
686 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
687 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
688 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
689 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
693 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
694 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
695 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
696 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
698 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
700 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
701 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
702 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
703 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
704 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
714 void XGINew_DDR2x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
716 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
717 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
718 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
719 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
721 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
722 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
723 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
724 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
725 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
727 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
729 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
730 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
731 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
732 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
733 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
734 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
744 unsigned long P3c4, struct vb_device_info *pVBInfo)
746 unsigned long P3d4 = P3c4 + 0x10 ;
756 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
757 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
758 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
760 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
763 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
764 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
765 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
767 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
770 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
771 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
772 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
774 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
777 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
778 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
779 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
781 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
782 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
785 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
787 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
789 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
790 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
791 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
794 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
797 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
798 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
799 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
801 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
804 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
805 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
806 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
808 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
811 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
823 unsigned long P3c4, struct vb_device_info *pVBInfo)
825 unsigned long P3d4 = P3c4 + 0x10 ;
833 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
834 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
835 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
836 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
838 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
839 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
840 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
841 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
843 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
844 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
845 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
846 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
848 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
849 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
850 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
851 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
852 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
855 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
857 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
860 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
861 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
862 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
863 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
864 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
876 unsigned long P3c4, struct vb_device_info *pVBInfo)
878 unsigned long P3d4 = P3c4 + 0x10 ;
885 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
886 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
888 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
890 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
892 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
893 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
895 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
897 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
900 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
901 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
903 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
905 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
907 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
908 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
910 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
912 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
915 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
917 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
920 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
921 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
923 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
925 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
927 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
928 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
930 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
932 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
934 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
935 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
937 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
939 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
942 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
944 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
958 P3c4 = Port - 0x10 ;
970 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1004 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1019 P3c4 = Port - 0x10 ;
1057 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1071 P3c4 = Port - 0x10 ;
1094 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1096 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1113 P3c4 = Port - 0x10 ;
1222 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1223 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1225 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1229 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1230 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1240 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1260 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1263 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1265 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1267 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1269 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1271 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1273 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1275 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1277 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1282 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1290 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1295 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1302 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1331 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1333 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1335 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1339 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1342 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1374 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1375 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1378 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1380 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1382 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1383 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1410 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1411 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1413 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1415 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1417 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1420 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short)(data | 0x0F)); /* assume lowest speed DRAM */
1441 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
1444 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1445 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1467 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1493 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1495 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1497 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1500 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1502 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1536 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1538 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1552 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1570 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1590 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1607 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1628 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1629 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1649 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1650 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (unsigned short)(data & 0xFD));
1658 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1659 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1668 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1669 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1698 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1703 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1736 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1778 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1818 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1963 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1966 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1967 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1969 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
2077 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2100 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2104 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2128 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2151 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2156 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2216 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2250 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2251 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2259 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2260 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2271 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2272 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2289 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2298 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2299 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2311 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2312 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2335 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2341 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2352 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2358 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2363 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2370 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2376 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2381 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2387 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2394 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2399 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2416 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2422 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2423 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2428 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2429 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2443 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2450 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2464 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2475 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2476 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2490 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2497 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2498 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2518 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2602 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2603 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2604 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2608 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2609 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2610 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2619 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
2685 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2796 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
2799 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2800 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2801 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2802 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2805 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2806 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2807 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2808 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2810 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2811 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2812 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
2813 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2814 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2816 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
2818 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2819 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2820 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
2821 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2822 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2823 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
2841 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2864 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2866 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2868 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2880 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2903 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2905 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2906 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
2908 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2909 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
2924 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2947 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2949 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2951 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;