Lines Matching defs:pHwData
823 * pHwData - The pHwData structure
830 void Uxx_ReadEthernetAddress(struct hw_data *pHwData)
838 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */
839 Wb35Reg_ReadSync(pHwData, 0x03b4, <mp);
840 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16) ltmp);
841 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */
842 Wb35Reg_ReadSync(pHwData, 0x03b4, <mp);
843 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16) ltmp);
844 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */
845 Wb35Reg_ReadSync(pHwData, 0x03b4, <mp);
846 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16) ltmp);
847 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
848 Wb35Reg_WriteSync(pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress));
849 Wb35Reg_WriteSync(pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress + 4)));
883 void Uxx_power_on_procedure(struct hw_data *pHwData)
887 if (pHwData->phy_type <= RF_MAXIM_V1)
888 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xffffff38);
890 Wb35Reg_WriteSync(pHwData, 0x03f4, 0xFF5807FF);
891 Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
893 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */
896 if ((pHwData->phy_type == RF_WB_242) ||
897 (RF_WB_242_1 == pHwData->phy_type))
900 Wb35Reg_WriteSync(pHwData, 0x03d0, ltmp);
901 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
904 Wb35Reg_ReadSync(pHwData, 0x03d0, <mp);
908 if (!Wb35Reg_ReadSync(pHwData, 0x03d0, <mp))
912 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
915 Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
919 Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff);
922 void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp , char number)
927 pHwData->phy_para[i] = al7230_rf_data_24[i];
932 void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, char number)
937 pHwData->phy_para[i] = al7230_rf_data_50[i];
948 void RFSynthesizer_initial(struct hw_data *pHwData)
966 switch (pHwData->phy_type) {
971 pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */
978 pHwData->phy_para[i] = max2827_rf_data[i];
985 pHwData->phy_para[i] = max2828_rf_data[i];
992 pHwData->phy_para[i] = max2829_rf_data[i];
999 pHwData->phy_para[i] = al2230_rf_data[i];
1006 pHwData->phy_para[i] = al2230s_rf_data[i];
1012 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
1017 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1026 ltmp |= pHwData->VCO_trim << 4;
1029 pHwData->phy_para[i] = ltmp;
1035 pHwData->phy_number = number;
1040 Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
1048 Wb35Reg_WriteSync(pHwData, 0x864, pltmp[i]);
1051 if (pHwData->CalOneTime)
1053 pHwData->CalOneTime = 1;
1055 switch (pHwData->phy_type) {
1058 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1061 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1064 Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
1066 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
1068 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
1069 Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
1075 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1077 ltmp = pHwData->reg.BB5C & 0xfffff000;
1078 Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1079 pHwData->reg.BB50 |= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */
1080 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1084 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1088 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1092 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ;
1094 Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
1095 pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1096 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1100 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1107 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1110 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1113 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1117 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
1123 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1126 Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
1129 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1135 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1138 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1141 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1147 ltmp = pHwData->reg.BB5C & 0xfffff000;
1148 Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1149 Wb35Reg_WriteSync(pHwData, 0x1058, 0);
1150 pHwData->reg.BB50 |= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1151 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1156 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1160 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1166 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1169 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1172 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1175 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1179 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1184 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1187 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1190 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1193 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1197 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1202 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1208 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1211 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1216 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1219 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1223 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1228 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1231 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1235 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1240 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1243 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1247 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1252 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1255 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1259 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1262 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1267 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1273 void BBProcessor_AL7230_2400(struct hw_data *pHwData)
1275 struct wb35_reg *reg = &pHwData->reg;
1292 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1311 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1314 void BBProcessor_AL7230_5000(struct hw_data *pHwData)
1316 struct wb35_reg *reg = &pHwData->reg;
1333 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1351 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1362 * pHwData - Handle of the USB Device.
1368 void BBProcessor_initial(struct hw_data *pHwData)
1370 struct wb35_reg *reg = &pHwData->reg;
1373 switch (pHwData->phy_type) {
1386 pltmp[10] = (pHwData->phy_type == 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */
1389 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1408 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1410 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1430 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1449 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1451 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1469 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1488 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1489 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1506 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1527 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1529 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1546 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1567 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1569 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1572 BBProcessor_AL7230_2400(pHwData);
1574 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1592 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1598 pltmp[3] = pHwData->BB3c_cal; /* 0x103c 11a TX LS filter */
1599 reg->BB3C = pHwData->BB3c_cal;
1608 pltmp[9] = pHwData->BB54_cal; /* 0x1054 */
1609 reg->BB54 = pHwData->BB54_cal;
1613 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1615 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1630 void set_tx_power_per_channel_max2829(struct hw_data *pHwData, struct chan_info Channel)
1632 RFSynthesizer_SetPowerIndex(pHwData, 100);
1635 void set_tx_power_per_channel_al2230(struct hw_data *pHwData, struct chan_info Channel)
1639 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1640 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1642 RFSynthesizer_SetPowerIndex(pHwData, index);
1645 void set_tx_power_per_channel_al7230(struct hw_data *pHwData, struct chan_info Channel)
1652 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1653 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1657 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) {
1658 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1659 index = pHwData->TxVgaFor50[i].TxVgaValue;
1665 RFSynthesizer_SetPowerIndex(pHwData, index);
1668 void set_tx_power_per_channel_wb242(struct hw_data *pHwData, struct chan_info Channel)
1675 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1676 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1681 RFSynthesizer_SetPowerIndex(pHwData, index);
1692 * pHwData - Handle of the USB Device.
1699 void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info Channel)
1701 struct wb35_reg *reg = &pHwData->reg;
1707 switch (pHwData->phy_type) {
1714 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1716 RFSynthesizer_SetPowerIndex(pHwData, 100);
1722 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1727 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1729 RFSynthesizer_SetPowerIndex(pHwData, 100);
1735 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1740 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1742 RFSynthesizer_SetPowerIndex(pHwData, 100);
1748 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1756 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1760 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1763 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1768 set_tx_power_per_channel_max2829(pHwData, Channel);
1775 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1777 set_tx_power_per_channel_al2230(pHwData, Channel);
1781 if (Channel.band != pHwData->band) {
1784 BBProcessor_AL7230_2400(pHwData);
1787 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1790 BBProcessor_AL7230_5000(pHwData);
1793 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1797 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT);
1806 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1811 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1814 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1823 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1827 set_tx_power_per_channel_al7230(pHwData, Channel);
1834 Wb35Reg_Write(pHwData, 0x864, ltmp);
1836 set_tx_power_per_channel_wb242(pHwData, Channel);
1843 Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1846 Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1849 Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1861 Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1865 if (pHwData->phy_type != RF_AIROHA_7230) {
1868 Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1872 Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1881 u8 RFSynthesizer_SetPowerIndex(struct hw_data *pHwData, u8 PowerIndex)
1883 u32 Band = pHwData->band;
1886 if (pHwData->power_index == PowerIndex)
1889 if (RF_MAXIM_2825 == pHwData->phy_type) {
1891 index = RFSynthesizer_SetMaxim2825Power(pHwData, PowerIndex);
1892 } else if (RF_MAXIM_2827 == pHwData->phy_type) {
1894 index = RFSynthesizer_SetMaxim2827_24Power(pHwData, PowerIndex);
1896 index = RFSynthesizer_SetMaxim2827_50Power(pHwData, PowerIndex);
1897 } else if (RF_MAXIM_2828 == pHwData->phy_type) {
1899 index = RFSynthesizer_SetMaxim2828_24Power(pHwData, PowerIndex);
1901 index = RFSynthesizer_SetMaxim2828_50Power(pHwData, PowerIndex);
1902 } else if (RF_AIROHA_2230 == pHwData->phy_type) {
1904 index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1906 } else if (RF_AIROHA_2230S == pHwData->phy_type) {
1908 index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1910 } else if (RF_AIROHA_7230 == pHwData->phy_type) {
1912 index = RFSynthesizer_SetAiroha7230Power(pHwData, PowerIndex);
1914 } else if ((RF_WB_242 == pHwData->phy_type) ||
1915 (RF_WB_242_1 == pHwData->phy_type)) {
1917 index = RFSynthesizer_SetWinbond242Power(pHwData, PowerIndex);
1921 pHwData->power_index = index; /* Backup current */
1926 u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *pHwData, u8 index)
1932 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1936 u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *pHwData, u8 index)
1942 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1946 u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *pHwData, u8 index)
1952 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1956 u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *pHwData, u8 index)
1962 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1966 u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *pHwData, u8 index)
1972 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1976 u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index)
1990 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1994 u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index)
2007 Wb35Reg_Write(pHwData, 0x0864, PowerData);
2011 u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index)
2026 Wb35Reg_Write(pHwData, 0x0864, PowerData);
2029 Wb35Reg_Write(pHwData, 0x1048, w89rf242_txvga_data[i][2]);
2030 Wb35Reg_Write(pHwData, 0x104c, w89rf242_txvga_data[i][3]);
2031 Wb35Reg_Write(pHwData, 0x1058, w89rf242_txvga_data[i][4]);
2045 void Dxx_initial(struct hw_data *pHwData)
2047 struct wb35_reg *reg = &pHwData->reg;
2055 if (!HAL_USB_MODE_BURST(pHwData))
2058 Wb35Reg_WriteSync(pHwData, 0x0400, reg->D00_DmaControl);
2061 void Mxx_initial(struct hw_data *pHwData)
2063 struct wb35_reg *reg = &pHwData->reg;
2089 pHwData->cwmin = DEFAULT_CWMIN;
2090 pHwData->cwmax = DEFAULT_CWMAX;
2096 pltmp[3] = *(u32 *)pHwData->bssid;
2099 pHwData->AID = DEFAULT_AID;
2100 tmp = *(u16 *) (pHwData->bssid + 4);
2114 pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2125 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2126 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2136 Wb35Reg_WriteSync(pHwData, 0x0824 + i * 4, pltmp[i]);
2139 Wb35Reg_WriteSync(pHwData, 0x0860, 0x12481248);
2143 Wb35Reg_WriteSync(pHwData, 0x0868, 0x00050900);
2147 Wb35Reg_WriteSync(pHwData, 0x0898, 0xffff8888);
2152 void Uxx_power_off_procedure(struct hw_data *pHwData)
2155 Wb35Reg_WriteSync(pHwData, 0x03b0, 3);
2156 Wb35Reg_WriteSync(pHwData, 0x03f0, 0xf9);
2160 void GetTxVgaFromEEPROM(struct hw_data *pHwData)
2169 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000 + 0x00010000 * i);
2170 Wb35Reg_ReadSync(pHwData, 0x03b4, <mp);
2185 if (pHwData->phy_type == RF_WB_242) {
2199 memcpy(pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM * 2); /* MAX_TXVGA_EEPROM is u16 count */
2200 EEPROMTxVgaAdjust(pHwData);
2209 void EEPROMTxVgaAdjust(struct hw_data *pHwData)
2211 u8 *pTxVga = pHwData->TxVgaSettingInEEPROM;
2218 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp * i / 4;
2222 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp * (i - 5) / 4;
2226 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp * (i - 10) / 2;
2228 pHwData->TxVgaFor24[13] = pTxVga[3];
2231 if (pHwData->phy_type == RF_AIROHA_7230) {
2233 pHwData->TxVgaFor50[0].ChanNo = 184;
2234 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2236 pHwData->TxVgaFor50[3].ChanNo = 196;
2237 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2239 pHwData->TxVgaFor50[1].ChanNo = 188;
2240 pHwData->TxVgaFor50[2].ChanNo = 192;
2242 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp / 3;
2243 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp * 2 / 3;
2246 pHwData->TxVgaFor50[6].ChanNo = 16;
2247 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2248 pHwData->TxVgaFor50[4].ChanNo = 8;
2249 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2250 pHwData->TxVgaFor50[5].ChanNo = 12;
2251 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2254 pHwData->TxVgaFor50[8].ChanNo = 36;
2255 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2256 pHwData->TxVgaFor50[7].ChanNo = 34;
2257 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2258 pHwData->TxVgaFor50[9].ChanNo = 38;
2259 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2262 pHwData->TxVgaFor50[10].ChanNo = 40;
2263 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2265 pHwData->TxVgaFor50[14].ChanNo = 48;
2266 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2268 pHwData->TxVgaFor50[11].ChanNo = 42;
2269 pHwData->TxVgaFor50[12].ChanNo = 44;
2270 pHwData->TxVgaFor50[13].ChanNo = 46;
2272 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp / 4;
2273 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp * 2 / 4;
2274 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp * 3 / 4;
2277 pHwData->TxVgaFor50[15].ChanNo = 52;
2278 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2280 pHwData->TxVgaFor50[18].ChanNo = 64;
2281 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2283 pHwData->TxVgaFor50[16].ChanNo = 56;
2284 pHwData->TxVgaFor50[17].ChanNo = 60;
2286 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp / 3;
2287 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp * 2 / 3;
2290 pHwData->TxVgaFor50[19].ChanNo = 100;
2291 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2293 pHwData->TxVgaFor50[22].ChanNo = 112;
2294 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2296 pHwData->TxVgaFor50[20].ChanNo = 104;
2297 pHwData->TxVgaFor50[21].ChanNo = 108;
2299 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp / 3;
2300 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp * 2 / 3;
2303 pHwData->TxVgaFor50[26].ChanNo = 128;
2304 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2306 pHwData->TxVgaFor50[23].ChanNo = 116;
2307 pHwData->TxVgaFor50[24].ChanNo = 120;
2308 pHwData->TxVgaFor50[25].ChanNo = 124;
2310 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp / 4;
2311 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp * 2 / 4;
2312 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp * 3 / 4;
2315 pHwData->TxVgaFor50[29].ChanNo = 140;
2316 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2318 pHwData->TxVgaFor50[27].ChanNo = 132;
2319 pHwData->TxVgaFor50[28].ChanNo = 136;
2321 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp / 3;
2322 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp * 2 / 3;
2325 pHwData->TxVgaFor50[30].ChanNo = 149;
2326 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2328 pHwData->TxVgaFor50[34].ChanNo = 165;
2329 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2331 pHwData->TxVgaFor50[31].ChanNo = 153;
2332 pHwData->TxVgaFor50[32].ChanNo = 157;
2333 pHwData->TxVgaFor50[33].ChanNo = 161;
2335 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp / 4;
2336 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4;
2337 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4;
2342 DataDmp((u8 *)pHwData->TxVgaFor24, 14 , 0);
2344 DataDmp((u8 *)pHwData->TxVgaFor50, 70 , 0);
2348 void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate)
2350 struct wb35_reg *reg = &pHwData->reg;
2354 switch (pHwData->phy_type) {
2360 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11B);
2361 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B);
2366 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11G);
2367 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G);
2377 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11B);
2378 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11B);
2385 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11G);
2386 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11G);