Lines Matching defs:phw_data
38 * void _phy_rf_write_delay(struct hw_data *phw_data);
39 * void phy_init_rf(struct hw_data *phw_data);
318 void _reset_rx_cal(struct hw_data *phw_data)
322 hw_get_dxx_reg(phw_data, 0x54, &val);
324 if (phw_data->revision == 0x2002) /* 1st-cut */
329 hw_set_dxx_reg(phw_data, 0x54, val);
338 void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
346 phy_init_rf(phw_data);
349 if ((RF_WB_242 == phw_data->phy_type) ||
350 (RF_WB_242_1 == phw_data->phy_type)) /* 20060619.5 Add */{
354 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
362 hw_get_dxx_reg(phw_data, 0x5C, &val);
364 hw_set_dxx_reg(phw_data, 0x5C, val);
367 hw_set_dxx_reg(phw_data, 0x3C, 0);
368 hw_set_dxx_reg(phw_data, 0x54, 0);
370 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
373 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
376 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
378 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
380 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
383 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl);
385 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
387 hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl);
389 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
394 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
396 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
399 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
403 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
412 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
414 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
417 /* hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); */
419 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
421 /* hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); */
423 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
426 /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
429 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
433 void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
452 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
454 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
456 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
458 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
460 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
462 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
465 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
468 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
470 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
472 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
475 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
488 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
491 hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
500 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
502 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
515 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
517 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
548 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
553 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
558 void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
574 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
576 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
578 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
580 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
582 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
584 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
587 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
590 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
592 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
594 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
597 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
603 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
606 hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
615 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
617 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
630 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
632 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
663 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
669 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
674 u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
707 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
717 if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) /* 20060718.1 modify */
728 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
732 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
747 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
754 /* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */
755 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
758 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
762 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
803 phw_data->iq_rsdl_gain_tx_d2 = a_2;
804 phw_data->iq_rsdl_phase_tx_d2 = b_2;
842 if (phw_data->revision == 0x2002) /* 1st-cut */
877 if (phw_data->revision == 0x2002) /* 1st-cut */{
878 hw_get_dxx_reg(phw_data, 0x54, &val);
885 hw_get_dxx_reg(phw_data, 0x3C, &val);
899 if (phw_data->revision == 0x2002) /* 1st-cut */{
926 if (phw_data->revision == 0x2002) /* 1st-cut */{
932 hw_set_dxx_reg(phw_data, 0x54, val);
941 hw_set_dxx_reg(phw_data, 0x3C, val);
948 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
957 void _tx_iq_calibration_winbond(struct hw_data *phw_data)
971 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
973 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */
975 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */
977 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */
979 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
983 /* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */
987 adjust_TXVGA_for_iq_mag(phw_data);
990 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
993 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
995 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
997 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
999 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
1002 if (phw_data->revision == 0x2002) /* 1st-cut */{
1003 hw_get_dxx_reg(phw_data, 0x54, &val);
1005 hw_set_dxx_reg(phw_data, 0x54, val);
1007 hw_get_dxx_reg(phw_data, 0x3C, &val);
1009 hw_set_dxx_reg(phw_data, 0x3C, val);
1012 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
1015 if (phw_data->revision == 0x2002) /* 1st-cut */{
1016 hw_get_dxx_reg(phw_data, 0x54, &val);
1018 hw_set_dxx_reg(phw_data, 0x54, val);
1020 hw_get_dxx_reg(phw_data, 0x3C, &val);
1022 hw_set_dxx_reg(phw_data, 0x3C, val);
1025 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
1027 if (phw_data->revision == 0x2002) /* 1st-cut */{
1028 hw_get_dxx_reg(phw_data, 0x54, &val);
1030 hw_set_dxx_reg(phw_data, 0x54, val);
1032 hw_get_dxx_reg(phw_data, 0x3C, &val);
1034 hw_set_dxx_reg(phw_data, 0x3C, val);
1038 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
1045 if (phw_data->revision == 0x2002) /* 1st-cut */{
1046 hw_get_dxx_reg(phw_data, 0x54, &val);
1048 hw_set_dxx_reg(phw_data, 0x54, val);
1050 hw_get_dxx_reg(phw_data, 0x3C, &val);
1052 hw_set_dxx_reg(phw_data, 0x3C, val);
1060 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
1062 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1066 /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
1069 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1072 if (phw_data->revision == 0x2002) /* 1st-cut */{
1073 hw_get_dxx_reg(phw_data, 0x54, &val);
1080 hw_get_dxx_reg(phw_data, 0x3C, &val);
1103 u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
1137 hw_get_cxx_reg(phw_data, 0x80, &val);
1139 hw_set_cxx_reg(phw_data, 0x80, val);
1142 hw_get_cxx_reg(phw_data, 0xE4, &val);
1144 hw_set_cxx_reg(phw_data, 0xE4, val);
1147 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); /* IQ_Alpha */
1151 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
1170 if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */
1176 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1180 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1188 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
1235 phw_data->iq_rsdl_gain_tx_d2;
1237 phw_data->iq_rsdl_phase_tx_d2;
1239 PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2));
1240 PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2));
1260 if (phw_data->revision == 0x2002)/* 1st-cut */
1308 hw_get_dxx_reg(phw_data, 0x54, &val);
1311 if (phw_data->revision == 0x2002) /* 1st-cut */{
1328 if (phw_data->revision == 0x2002) /* 1st-cut */{
1355 hw_get_dxx_reg(phw_data, 0x54, &val);
1356 if (phw_data->revision == 0x2002) /* 1st-cut */{
1362 hw_set_dxx_reg(phw_data, 0x54, val);
1369 hw_set_dxx_reg(phw_data, 0x54, val);
1385 void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1399 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
1401 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
1403 phy_set_rf_data(phw_data, 5, (5<<24) | phw_data->txvga_setting_for_cal);
1405 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
1407 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
1413 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
1416 _reset_rx_cal(phw_data);
1417 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
1420 _reset_rx_cal(phw_data);
1421 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
1427 _reset_rx_cal(phw_data);
1433 hw_get_dxx_reg(phw_data, 0x54, &val);
1436 if (phw_data->revision == 0x2002) /* 1st-cut */{
1457 void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1465 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
1466 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
1467 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
1471 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
1472 /* _txidac_dc_offset_cancellation_winbond(phw_data); */
1473 /* _txqdac_dc_offset_cacellation_winbond(phw_data); */
1475 _tx_iq_calibration_winbond(phw_data);
1476 _rx_iq_calibration_winbond(phw_data, frequency);
1479 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
1481 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1485 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
1486 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
1487 hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
1491 phy_init_rf(phw_data);
1537 unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
1553 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga));
1554 phw_data->txvga_setting_for_cal = current_txvga;
1558 if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl))/* 20060718.1 modify */
1571 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1579 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);