Lines Matching refs:dwIoBase
2010 * dwIoBase - I/O base address
2018 bool BBbReadEmbeded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
2024 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2027 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2030 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2036 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2052 * dwIoBase - I/O base address
2061 bool BBbWriteEmbeded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byData)
2067 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2069 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2072 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2075 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2094 * dwIoBase - I/O base address
2103 bool BBbIsRegBitsOn (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2107 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2117 * dwIoBase - I/O base address
2126 bool BBbIsRegBitsOff (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2130 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2139 * dwIoBase - I/O base address
2153 unsigned long dwIoBase = pDevice->PortOffset;
2160 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253InitTab_RFMD[ii][0],byVT3253InitTab_RFMD[ii][1]);
2164 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_RFMD[ii][0],byVT3253B0_RFMD[ii][1]);
2167 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC4_RFMD2959[ii][0],byVT3253B0_AGC4_RFMD2959[ii][1]);
2169 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2170 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2182 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2185 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2197 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2200 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2202 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2203 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2215 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2218 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2220 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2222 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2225 bResult &= BBbWriteEmbeded(dwIoBase,0x90,0x20);
2226 bResult &= BBbWriteEmbeded(dwIoBase,0x97,0xeb);
2230 bResult &= BBbWriteEmbeded(dwIoBase,0xa6,0x00);
2231 bResult &= BBbWriteEmbeded(dwIoBase,0xa8,0x30);
2233 bResult &= BBbWriteEmbeded(dwIoBase,0xb0,0x58);
2236 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2238 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2239 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2253 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2256 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2267 MACvSetRFLE_LatchBase(dwIoBase);
2271 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2276 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2278 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2280 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2284 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2302 BBbWriteEmbeded(dwIoBase, 0x04, 0x7F);
2303 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);
2316 * dwIoBase - I/O base address
2324 void BBvReadAllRegs (unsigned long dwIoBase, unsigned char *pbyBBRegs)
2329 BBbReadEmbeded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2339 * dwIoBase - I/O base address
2352 unsigned long dwIoBase = pDevice->PortOffset;
2355 BBbReadEmbeded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2356 BBbWriteEmbeded(dwIoBase, 0xC9, 0);
2357 BBbReadEmbeded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2358 BBbWriteEmbeded(dwIoBase, 0x4D, 0x90);
2361 BBbReadEmbeded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2365 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2366 BBbWriteEmbeded(dwIoBase, 0x21, (unsigned char)(byData | 0x01));//CR33
2368 BBbWriteEmbeded(dwIoBase, 0x9A, 0); //CR154
2370 BBbWriteEmbeded(dwIoBase, 0x88, 0x02);//CR239
2374 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2375 BBbWriteEmbeded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01));//CR154
2377 BBbWriteEmbeded(dwIoBase, 0x21, 0); //CR33
2379 BBbWriteEmbeded(dwIoBase, 0x88, 0x03);//CR239
2383 BBbWriteEmbeded(dwIoBase, 0x0E, 0);//CR14
2406 unsigned long dwIoBase = pDevice->PortOffset;
2408 BBbWriteEmbeded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2409 BBbWriteEmbeded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2410 BBbWriteEmbeded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2411 BBbWriteEmbeded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2415 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2416 BBbWriteEmbeded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE));//CR33
2419 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2420 BBbWriteEmbeded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE));//CR154
2422 BBbReadEmbeded(dwIoBase, 0x0E, &byData);//CR14
2423 BBbWriteEmbeded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80));//CR14
2490 * dwIoBase - I/O base address
2498 BBvSoftwareReset (unsigned long dwIoBase)
2500 BBbWriteEmbeded(dwIoBase, 0x50, 0x40);
2501 BBbWriteEmbeded(dwIoBase, 0x50, 0);
2502 BBbWriteEmbeded(dwIoBase, 0x9C, 0x01);
2503 BBbWriteEmbeded(dwIoBase, 0x9C, 0);
2511 * dwIoBase - I/O base address
2519 BBvPowerSaveModeON (unsigned long dwIoBase)
2523 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2525 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2533 * dwIoBase - I/O base address
2541 BBvPowerSaveModeOFF (unsigned long dwIoBase)
2545 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2547 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2565 BBvSetTxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2572 BBbReadEmbeded(dwIoBase, 0x09, &byBBTxConf);//CR09
2586 BBbWriteEmbeded(dwIoBase, 0x09, byBBTxConf);//CR09
2607 BBvSetRxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2611 BBbReadEmbeded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2621 BBbWriteEmbeded(dwIoBase, 0x0A, byBBRxConf);//CR10
2638 BBvSetDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2640 BBbWriteEmbeded(dwIoBase, 0x0C, 0x17);//CR12
2641 BBbWriteEmbeded(dwIoBase, 0x0D, 0xB9);//CR13
2645 BBvExitDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2647 BBbWriteEmbeded(dwIoBase, 0x0C, 0x00);//CR12
2648 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);//CR13