Lines Matching refs:aspace
476 vme_address_t aspace, unsigned long long address, size_t count)
503 vme_address_t aspace, unsigned long long address, size_t count)
530 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
546 switch (aspace) {
680 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
718 *aspace = 0;
726 *aspace |= VME_A16;
730 *aspace |= VME_A24;
734 *aspace |= VME_A32;
738 *aspace |= VME_A64;
876 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1026 switch (aspace) {
1107 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1146 *aspace = 0;
1155 *aspace |= VME_A16;
1157 *aspace |= VME_A24;
1159 *aspace |= VME_A32;
1161 *aspace |= VME_A64;
1163 *aspace |= VME_CRCSR;
1165 *aspace |= VME_USER1;
1167 *aspace |= VME_USER2;
1169 *aspace |= VME_USER3;
1171 *aspace |= VME_USER4;
1217 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1223 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1236 vme_address_t aspace;
1252 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1255 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1262 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1278 vme_address_t aspace;
1313 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1318 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1325 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1397 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1448 switch (aspace) {
1491 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1542 switch (aspace) {
1660 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1698 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1853 vme_address_t aspace, vme_cycle_t cycle)
1876 switch (aspace) {
1920 vme_address_t *aspace, vme_cycle_t *cycle)
1939 *aspace |= VME_A16;
1942 *aspace |= VME_A24;
1945 *aspace |= VME_A32;
1948 *aspace |= VME_A64;