Lines Matching refs:TSI148_LCSR_OT
964 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
967 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1069 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1071 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1073 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1075 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1077 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1079 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1083 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1089 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1121 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1124 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1126 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1128 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1130 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1132 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1134 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1361 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1363 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
2517 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +