Lines Matching refs:iowrite32
192 iowrite32(stat, bridge->base + LINT_STAT);
214 iowrite32(0, bridge->base + VINT_EN);
217 iowrite32(0, bridge->base + LINT_EN);
219 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
230 iowrite32(0, bridge->base + LINT_MAP0);
231 iowrite32(0, bridge->base + LINT_MAP1);
232 iowrite32(0, bridge->base + LINT_MAP2);
239 iowrite32(tmp, bridge->base + LINT_EN);
248 iowrite32(0, bridge->base + VINT_EN);
251 iowrite32(0, bridge->base + LINT_EN);
253 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
279 iowrite32(tmp, bridge->base + LINT_EN);
306 iowrite32(statid << 24, bridge->base + STATID);
310 iowrite32(tmp, bridge->base + VINT_EN);
318 iowrite32(tmp, bridge->base + VINT_EN);
398 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
401 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
402 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
403 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
421 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
426 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
649 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
720 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
721 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
722 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
725 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
730 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
906 iowrite32(0, bridge->base + SCYC_CTL);
909 iowrite32(mask, bridge->base + SCYC_EN);
910 iowrite32(compare, bridge->base + SCYC_CMP);
911 iowrite32(swap, bridge->base + SCYC_SWP);
912 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
915 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
921 iowrite32(0, bridge->base + SCYC_CTL);
1124 iowrite32(0, bridge->base + DTBC);
1125 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1136 iowrite32(val, bridge->base + DGCS);
1140 iowrite32(val, bridge->base + DGCS);
1246 iowrite32(lm_base, bridge->base + LM_BS);
1247 iowrite32(lm_ctl, bridge->base + LM_CTL);
1333 iowrite32(tmp, bridge->base + LINT_EN);
1338 iowrite32(lm_ctl, bridge->base + LM_CTL);
1361 iowrite32(tmp, bridge->base + LINT_EN);
1363 iowrite32(CA91CX42_LINT_LM[monitor],
1374 iowrite32(tmp, bridge->base + LM_CTL);
1425 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1446 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1450 iowrite32(tmp, bridge->base + VCSR_CTL);
1466 iowrite32(tmp, bridge->base + VCSR_CTL);
1469 iowrite32(0, bridge->base + VCSR_TO);
1755 iowrite32(0, bridge->base + LINT_EN);
1758 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1759 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1760 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1761 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1762 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1763 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1764 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1765 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1766 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1767 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1768 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1769 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1770 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1771 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1772 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1773 iowrite32(0x00F00000, bridge->base + VSI7_CTL);