Lines Matching defs:intr_status
129 u32 intr_status[4] = {INTR_STATUS0, INTR_STATUS1,
141 FlashReg + intr_status[i]);
145 while (!(ioread32(FlashReg + intr_status[i]) &
148 if (ioread32(FlashReg + intr_status[i]) &
156 FlashReg + intr_status[i]);
823 u32 intr_status = 0;
839 intr_status = intr_status_addresses[flash_bank];
842 FlashReg + intr_status);
847 while (!(ioread32(FlashReg + intr_status) &
851 if (ioread32(FlashReg + intr_status) &
856 FlashReg + intr_status);
885 u32 intr_status = 0;
912 intr_status = intr_status_addresses[flash_bank];
913 iowrite32(ioread32(FlashReg + intr_status),
914 FlashReg + intr_status);
922 while (!(ioread32(FlashReg + intr_status) &
1094 u32 intr_status = 0;
1114 intr_status = intr_status_addresses[flash_bank];
1115 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1151 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1156 while (!(ioread32(FlashReg + intr_status) &
1161 if (ioread32(FlashReg + intr_status) &
1164 FlashReg + intr_status);
1169 if (ioread32(FlashReg + intr_status) &
1174 FlashReg + intr_status);
1175 else if (ioread32(FlashReg + intr_status) &
1178 FlashReg + intr_status);
1179 else if (ioread32(FlashReg + intr_status) &
1182 FlashReg + intr_status);
1184 while (!(ioread32(FlashReg + intr_status) &
1187 iowrite32(INTR_STATUS0__DMA_CMD_COMP, FlashReg + intr_status);
1190 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1206 u32 intr_status = 0;
1226 intr_status = intr_status_addresses[flash_bank];
1227 iowrite32(ioread32(FlashReg + intr_status),
1228 FlashReg + intr_status);
1243 while (!ioread32(FlashReg + intr_status))
1246 if (ioread32(FlashReg + intr_status) &
1249 FlashReg + intr_status);
1252 } else if (ioread32(FlashReg + intr_status) &
1255 FlashReg + intr_status);
1261 } else if (ioread32(FlashReg + intr_status) &
1265 FlashReg + intr_status);
1273 while (!(ioread32(FlashReg + intr_status) &
1278 FlashReg + intr_status);
1285 FlashReg + intr_status);
1289 iowrite32(ioread32(FlashReg + intr_status),
1290 FlashReg + intr_status);
1305 u32 intr_status = 0;
1326 intr_status = intr_status_addresses[flash_bank];
1327 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1363 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1386 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1504 u32 intr_status = 0;
1521 intr_status = intr_status_addresses[flash_bank];
1522 iowrite32(ioread32(FlashReg + intr_status),
1523 FlashReg + intr_status);
1538 while (!ioread32(FlashReg + intr_status))
1541 if (ioread32(FlashReg + intr_status) &
1544 FlashReg + intr_status);
1547 } else if (ioread32(FlashReg + intr_status) &
1550 FlashReg + intr_status);
1556 } else if (ioread32(FlashReg + intr_status) &
1560 FlashReg + intr_status);
1568 while (!(ioread32(FlashReg + intr_status) &
1572 FlashReg + intr_status);
1579 FlashReg + intr_status);
1583 iowrite32(ioread32(FlashReg + intr_status),
1584 FlashReg + intr_status);
1604 u32 intr_status = 0;
1626 intr_status = intr_status_addresses[flash_bank];
1627 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1659 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1675 u32 intr_status = 0;
1695 intr_status = intr_status_addresses[flash_bank];
1700 INTR_STATUS0__PROGRAM_FAIL, FlashReg + intr_status);
1736 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1759 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1798 u32 intr_status = 0;
1813 intr_status = intr_status_addresses[flash_bank];
1823 iowrite32(ioread32(FlashReg + intr_status),
1824 FlashReg + intr_status);
1879 while (!(ioread32(FlashReg + intr_status) &
1884 if (ioread32(FlashReg + intr_status) &
1888 iowrite32(ioread32(FlashReg + intr_status),
1889 FlashReg + intr_status);
1916 u32 intr_status = 0;
1932 intr_status = intr_status_addresses[flash_bank];
1936 iowrite32(ioread32(FlashReg + intr_status),
1937 FlashReg + intr_status);
1952 while (!(ioread32(FlashReg + intr_status) &
2004 while (!(ioread32(FlashReg + intr_status) &
2009 if (ioread32(FlashReg + intr_status) &
2012 FlashReg + intr_status);
2017 if (ioread32(FlashReg + intr_status) &
2022 FlashReg + intr_status);
2023 } else if (ioread32(FlashReg + intr_status) &
2027 FlashReg + intr_status);
2028 } else if (ioread32(FlashReg + intr_status) &
2031 FlashReg + intr_status);
2056 u32 intr_status = 0;
2078 intr_status = intr_status_addresses[flash_bank];
2079 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2111 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2128 u32 intr_status = 0;
2147 intr_status = intr_status_addresses[flash_bank];
2148 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2165 while (!ioread32(FlashReg + intr_status))
2168 if (ioread32(FlashReg + intr_status) &
2171 FlashReg + intr_status);
2176 } else if (ioread32(FlashReg + intr_status) &
2180 t = ioread32(FlashReg + intr_status) &
2182 iowrite32(t, FlashReg + intr_status);
2186 FlashReg + intr_status);
2190 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2227 u32 intr_status;
2234 intr_status = intr_status_addresses[dev->flash_bank];
2238 if (ioread32(FlashReg + intr_status) &
2241 FlashReg + intr_status);
2245 } else if (ioread32(FlashReg + intr_status) &
2248 FlashReg + intr_status);
2252 } else if (ioread32(FlashReg + intr_status) &
2255 FlashReg + intr_status);
2261 if (ioread32(FlashReg + intr_status) &
2264 FlashReg + intr_status);
2269 intr_status,
2270 ioread32(FlashReg + intr_status));
2277 FlashReg + intr_status);
2283 u32 intr_status;
2292 intr_status = intr[dev->flash_bank];
2295 while (!ioread32(FlashReg + intr_status))
2298 if (ioread32(FlashReg + intr_status) &
2301 FlashReg + intr_status);
2305 } else if (ioread32(FlashReg + intr_status) &
2309 FlashReg + intr_status);
2313 FlashReg + intr_status);