Lines Matching refs:pCurrTxRate
1849 struct rt_rtmp_tx_rate_switch *pCurrTxRate, *pNextTxRate = NULL;
1984 pCurrTxRate =
1986 if ((pEntry->HTPhyMode.field.MCS != pCurrTxRate->CurrMCS)
1992 pCurrTxRate =
1996 MlmeSetTxRate(pAd, pEntry, pCurrTxRate);
2014 pCurrTxRate =
2017 if ((Rssi > -65) && (pCurrTxRate->Mode >= MODE_HTMIX)) {
2019 (pCurrTxRate->TrainUp +
2020 (pCurrTxRate->TrainUp >> 1));
2022 (pCurrTxRate->TrainDown +
2023 (pCurrTxRate->TrainDown >> 1));
2025 TrainUp = pCurrTxRate->TrainUp;
2026 TrainDown = pCurrTxRate->TrainDown;
2051 pCurrTxRate =
2055 if (pCurrTxRate->CurrMCS == MCS_0) {
2057 } else if (pCurrTxRate->CurrMCS == MCS_1) {
2059 } else if (pCurrTxRate->CurrMCS == MCS_2) {
2061 } else if (pCurrTxRate->CurrMCS == MCS_3) {
2063 } else if (pCurrTxRate->CurrMCS == MCS_4) {
2065 } else if (pCurrTxRate->CurrMCS == MCS_5) {
2067 } else if (pCurrTxRate->CurrMCS == MCS_6) {
2070 /*else if (pCurrTxRate->CurrMCS == MCS_7) */
2071 else if ((pCurrTxRate->CurrMCS == MCS_7) && (pCurrTxRate->ShortGI == GI_800)) /* prevent the highest MCS using short GI when 1T and low throughput */
2074 } else if (pCurrTxRate->CurrMCS == MCS_12) {
2076 } else if (pCurrTxRate->CurrMCS == MCS_13) {
2078 } else if (pCurrTxRate->CurrMCS == MCS_14) {
2081 else if ((pCurrTxRate->CurrMCS == MCS_15) && (pCurrTxRate->ShortGI == GI_800)) /*we hope to use ShortGI as initial rate, however Atheros's chip has bugs when short GI */
2084 } else if (pCurrTxRate->CurrMCS == MCS_20) /* 3*3 */
2087 } else if (pCurrTxRate->CurrMCS == MCS_21) {
2089 } else if (pCurrTxRate->CurrMCS == MCS_22) {
2091 } else if (pCurrTxRate->CurrMCS == MCS_23) {
2372 struct rt_rtmp_tx_rate_switch *pCurrTxRate, *pNextTxRate = NULL;
2423 pCurrTxRate =
2426 if ((Rssi > -65) && (pCurrTxRate->Mode >= MODE_HTMIX)) {
2428 (pCurrTxRate->TrainUp +
2429 (pCurrTxRate->TrainUp >> 1));
2431 (pCurrTxRate->TrainDown +
2432 (pCurrTxRate->TrainDown >> 1));
2434 TrainUp = pCurrTxRate->TrainUp;
2435 TrainDown = pCurrTxRate->TrainDown;