Lines Matching refs:block_id
31 #define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
33 #define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
35 #define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
37 #define CVMX_PCSXX_CONTROL1_REG(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
39 #define CVMX_PCSXX_CONTROL2_REG(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
41 #define CVMX_PCSXX_INT_EN_REG(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
43 #define CVMX_PCSXX_INT_REG(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
45 #define CVMX_PCSXX_LOG_ANL_REG(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
47 #define CVMX_PCSXX_MISC_CTL_REG(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
49 #define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
51 #define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
53 #define CVMX_PCSXX_STATUS1_REG(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
55 #define CVMX_PCSXX_STATUS2_REG(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
57 #define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
59 #define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))