Lines Matching refs:block_id
31 #define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
33 #define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
35 #define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
37 #define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
39 #define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
41 #define CVMX_PCSX_INTX_REG(offset, block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
43 #define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
45 #define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
47 #define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
49 #define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
51 #define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
53 #define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
55 #define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
57 #define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
59 #define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
61 #define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
63 #define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))