Lines Matching defs:interface
44 void __cvmx_interrupt_gmxx_enable(int interface);
48 * Probe a XAUI interface and determine the number of ports
49 * connected to it. The XAUI interface should still be down
52 * @interface: Interface to probe
54 * Returns Number of ports on the interface. Zero to disable.
56 int __cvmx_helper_xaui_probe(int interface)
64 * interface needs to be enabled before IPD otherwise per port
67 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
69 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
71 __cvmx_helper_setup_gmx(interface, 1);
76 * interface to the XAUI. This allows us to use HiGig2
89 pko_mem_port_ptrs.s.eid = interface * 4;
90 pko_mem_port_ptrs.s.pid = interface * 16 + i;
95 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
103 * Bringup and enable a XAUI interface. After this call packet
107 * @interface: Interface to bring up
111 int __cvmx_helper_xaui_enable(int interface)
124 xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
126 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
129 gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
130 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
131 gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
132 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
133 pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
134 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
139 gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
143 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
146 xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
149 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
153 (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
158 (CVMX_PCSXX_10GBX_STATUS_REG(interface),
163 (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
168 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
170 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
174 (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
179 (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
184 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
188 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
189 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
190 cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
191 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
194 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
195 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
196 cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
197 cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
198 cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
199 cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
203 (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
207 (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
211 (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
215 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
216 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
217 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
219 cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
223 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
225 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
227 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
229 __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
230 __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
231 __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
232 __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
233 __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
234 __cvmx_interrupt_gmxx_enable(interface);
251 int interface = cvmx_helper_get_interface_num(ipd_port);
257 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
258 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
260 cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
271 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
272 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
273 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
292 int interface = cvmx_helper_get_interface_num(ipd_port);
296 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
297 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
308 return __cvmx_helper_xaui_enable(interface);
328 int interface = cvmx_helper_get_interface_num(ipd_port);
334 cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
336 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
341 cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
343 cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
347 return __cvmx_helper_xaui_enable(interface);