Lines Matching refs:DISP_POWER_CTL_1_ADDR
150 #define DISP_POWER_CTL_1_ADDR 0x100
151 DISP_REG(DISP_POWER_CTL_1_ADDR)
367 /* DISP_POWER_CTL_1_ADDR Power Control (1) */
821 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFEE);
823 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xF812);
825 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xE811);
827 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC011);
829 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x4011);
831 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0010);
835 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFE);
838 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BED);
841 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x00CD);
928 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC010);
932 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFFE);
969 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0801);
992 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0881);
996 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BE1);
1000 DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFF);