Lines Matching defs:etdev
97 static void et131x_xcvr_init(struct et131x_adapter *etdev);
101 * @etdev: pointer to our private adapter structure
108 int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
111 struct _MAC_t __iomem *mac = &etdev->regs->mac;
143 dev_warn(&etdev->pdev->dev,
145 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
167 int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
169 struct _MAC_t __iomem *mac = &etdev->regs->mac;
171 u8 xcvrAddr = etdev->Stats.xcvr_addr;
203 dev_warn(&etdev->pdev->dev,
205 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
207 dev_warn(&etdev->pdev->dev, "command is 0x%08x\n",
210 MiRead(etdev, xcvrReg, &TempValue);
228 * @etdev: pointer to our private adapter structure
232 int et131x_xcvr_find(struct et131x_adapter *etdev)
242 PhyMiRead(etdev, xcvr_addr,
245 PhyMiRead(etdev, xcvr_addr,
252 etdev->Stats.xcvr_id = xcvr_id;
253 etdev->Stats.xcvr_addr = xcvr_addr;
260 void ET1310_PhyReset(struct et131x_adapter *etdev)
262 MiWrite(etdev, PHY_CONTROL, 0x8000);
267 * @etdev: device to control
276 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
280 MiRead(etdev, PHY_CONTROL, &data);
284 MiWrite(etdev, PHY_CONTROL, data);
289 * @etdev: device to control
296 static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
300 MiRead(etdev, PHY_CONTROL, &data);
304 MiWrite(etdev, PHY_CONTROL, data);
309 * @etdev: device to control
315 static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
319 MiRead(etdev, PHY_CONTROL, &data);
323 MiWrite(etdev, PHY_CONTROL, data);
328 * @etdev: device to control
334 static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
340 MiRead(etdev, PHY_CONTROL, &data);
344 MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
349 * @etdev: device to read
364 static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
377 MiRead(etdev, PHY_STATUS, &mistatus);
378 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
379 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
380 MiRead(etdev, PHY_CONTROL, &control);
398 static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
403 MiRead(etdev, regnum, ®);
406 MiWrite(etdev, regnum, reg);
410 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
417 MiRead(etdev, regnum, ®);
425 MiWrite(etdev, regnum, reg | mask);
429 MiWrite(etdev, regnum, reg & ~mask);
437 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
443 MiRead(etdev, PHY_1000_CONTROL, &data);
470 MiWrite(etdev, PHY_1000_CONTROL, data);
473 static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
479 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
507 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
510 static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
516 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
544 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
549 * @etdev: pointer to our private adapter structure
555 void et131x_setphy_normal(struct et131x_adapter *etdev)
558 ET1310_PhyPowerDown(etdev, 0);
559 et131x_xcvr_init(etdev);
565 * @etdev: pointer to our private adapter structure
568 static void et131x_xcvr_init(struct et131x_adapter *etdev)
575 etdev->Bmsr.value = 0;
577 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
578 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
587 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
597 if ((etdev->eepromData[1] & 0x4) == 0) {
598 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
600 if ((etdev->eepromData[1] & 0x8) == 0)
605 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
610 if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
611 if (etdev->RegistryFlowControl == TxOnly ||
612 etdev->RegistryFlowControl == Both)
613 ET1310_PhyAccessMiBit(etdev,
616 ET1310_PhyAccessMiBit(etdev,
619 if (etdev->RegistryFlowControl == Both)
620 ET1310_PhyAccessMiBit(etdev,
623 ET1310_PhyAccessMiBit(etdev,
627 ET1310_PhyAutoNeg(etdev, true);
630 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
634 ET1310_PhyAutoNeg(etdev, false);
637 if (etdev->AiForceDpx != 1) {
638 if (etdev->RegistryFlowControl == TxOnly ||
639 etdev->RegistryFlowControl == Both)
640 ET1310_PhyAccessMiBit(etdev,
643 ET1310_PhyAccessMiBit(etdev,
646 if (etdev->RegistryFlowControl == Both)
647 ET1310_PhyAccessMiBit(etdev,
650 ET1310_PhyAccessMiBit(etdev,
653 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
654 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
656 ET1310_PhyPowerDown(etdev, 1);
657 switch (etdev->AiForceSpeed) {
660 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
661 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
662 if (etdev->AiForceDpx == 1) {
664 ET1310_PhyAdvertise10BaseT(etdev,
666 } else if (etdev->AiForceDpx == 2) {
668 ET1310_PhyAdvertise10BaseT(etdev,
672 ET1310_PhyAutoNeg(etdev, false);
674 ET1310_PhyAdvertise10BaseT(etdev,
677 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
679 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
684 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
685 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
686 if (etdev->AiForceDpx == 1) {
688 ET1310_PhyAdvertise100BaseT(etdev,
691 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
692 } else if (etdev->AiForceDpx == 2) {
694 ET1310_PhyAdvertise100BaseT(etdev,
698 ET1310_PhyAutoNeg(etdev, false);
700 ET1310_PhyAdvertise100BaseT(etdev,
703 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
705 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
710 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
711 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
713 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
716 ET1310_PhyPowerDown(etdev, 0);
719 void et131x_Mii_check(struct et131x_adapter *etdev,
733 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
738 spin_lock_irqsave(&etdev->Lock, flags);
740 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
741 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
743 spin_unlock_irqrestore(&etdev->Lock, flags);
745 netif_carrier_on(etdev->netdev);
747 dev_warn(&etdev->pdev->dev,
750 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
753 * && TRU_QueryCoreType(etdev->hTruePhy, 0) ==
758 MiRead(etdev, 0x12, &Register18);
759 MiWrite(etdev, 0x12, Register18 | 0x4);
760 MiWrite(etdev, 0x10, Register18 | 0x8402);
761 MiWrite(etdev, 0x11, Register18 | 511);
762 MiWrite(etdev, 0x12, Register18);
771 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
772 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
773 spin_lock_irqsave(&etdev->Lock, flags);
774 etdev->MediaState =
776 spin_unlock_irqrestore(&etdev->Lock,
779 netif_carrier_off(etdev->netdev);
782 etdev->linkspeed = 0;
783 etdev->duplex_mode = 0;
786 et131x_free_busy_send_packets(etdev);
789 et131x_init_send(etdev);
792 et131x_reset_recv(etdev);
800 et131x_soft_reset(etdev);
803 et131x_adapter_setup(etdev);
808 if (etdev->RegistryPhyComa == 1)
809 EnablePhyComa(etdev);
814 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
815 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
816 ET1310_PhyLinkStatus(etdev,
821 etdev->linkspeed = speed;
822 etdev->duplex_mode = duplex;
824 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
826 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
830 * && TRU_QueryCoreType(etdev->hTruePhy, 0)==
835 MiRead(etdev, 0x12, &Register18);
836 MiWrite(etdev, 0x12, Register18 | 0x4);
837 MiWrite(etdev, 0x10, Register18 | 0x8402);
838 MiWrite(etdev, 0x11, Register18 | 511);
839 MiWrite(etdev, 0x12, Register18);
842 ConfigFlowControl(etdev);
844 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
845 etdev->RegistryJumboPacket > 2048)
846 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
849 SetRxDmaTimer(etdev);
850 ConfigMACRegs2(etdev);
902 void ET1310_PhyInit(struct et131x_adapter *etdev)
906 if (etdev == NULL)
910 MiRead(etdev, PHY_ID_1, &data);
911 MiRead(etdev, PHY_ID_2, &data);
914 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
915 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
919 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
920 MiRead(etdev, PHY_DATA_REG, &data);
923 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
926 MiRead(etdev, PHY_ID_1, &data);
927 MiRead(etdev, PHY_ID_2, &data);
930 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
931 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
935 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
936 MiRead(etdev, PHY_DATA_REG, &data);
938 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
941 MiRead(etdev, PHY_CONTROL, &data);
942 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
943 MiWrite(etdev, PHY_CONTROL, 0x1840);
945 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
951 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
952 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
955 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
956 MiRead(etdev, PHY_DATA_REG, &data);
963 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
964 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
965 MiWrite(etdev, PHY_CONTROL, 0x1040);
966 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);