Lines Matching refs:sram_ch
86 struct sram_channel *sram_ch =
120 *(rp++) = sram_ch->dma_ctl;
212 struct sram_channel *sram_ch =
222 tmp = cx_read(sram_ch->int_msk);
223 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
226 tmp = cx_read(sram_ch->dma_ctl);
227 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
272 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
384 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
470 struct sram_channel *sram_ch,
521 ret = cx25821_openfile_ch2(dev, sram_ch);
628 struct sram_channel *sram_ch;
635 sram_ch = dev->channels[channel_num].sram_channels;
637 msk_stat = cx_read(sram_ch->int_mstat);
638 vid_status = cx_read(sram_ch->int_stat);
692 struct sram_channel *sram_ch)
708 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
709 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
712 cx_write(sram_ch->gpcnt_ctl, 3);
715 cx_write(sram_ch->int_stat, _intr_msk);
718 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
719 tmp = cx_read(sram_ch->int_msk);
720 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
731 tmp = cx_read(sram_ch->dma_ctl);
732 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
747 struct sram_channel *sram_ch;
761 sram_ch = dev->channels[channel_select].sram_channels;
827 cx25821_sram_channel_setup_upstream(dev, sram_ch,
831 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
838 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
847 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);