Lines Matching refs:hw
348 static struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw)
353 if (!hw)
356 spin_lock_irqsave(&hw->lock, flags);
357 temp = hw->rx_pkt_pool_head;
359 hw->rx_pkt_pool_head = hw->rx_pkt_pool_head->next;
364 spin_unlock_irqrestore(&hw->lock, flags);
369 static void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw,
374 if (!hw || !pkt)
377 spin_lock_irqsave(&hw->lock, flags);
378 pkt->next = hw->rx_pkt_pool_head;
379 hw->rx_pkt_pool_head = pkt;
380 spin_unlock_irqrestore(&hw->lock, flags);
405 struct crystalhd_hw *hw = (struct crystalhd_hw *)context;
408 if (!pkt || !hw) {
409 BCMLOG_ERR("Invalid arg - %p %p\n", hw, pkt);
414 crystalhd_unmap_dio(hw->adp, pkt->dio_req);
418 crystalhd_hw_free_rx_pkt(hw, pkt);
427 static void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw)
429 if (!hw)
433 crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq);
434 crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq);
435 crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq);
436 crystalhd_hw_delete_ioq(hw->adp, hw->rx_freeq);
437 crystalhd_hw_delete_ioq(hw->adp, hw->rx_rdyq);
440 #define crystalhd_hw_create_ioq(sts, hw, q, cb) \
442 sts = crystalhd_create_dioq(hw->adp, &q, cb, hw); \
453 static enum BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw)
457 if (!hw) {
462 crystalhd_hw_create_ioq(sts, hw, hw->tx_freeq,
464 crystalhd_hw_create_ioq(sts, hw, hw->tx_actq,
467 crystalhd_hw_create_ioq(sts, hw, hw->rx_freeq,
469 crystalhd_hw_create_ioq(sts, hw, hw->rx_rdyq,
471 crystalhd_hw_create_ioq(sts, hw, hw->rx_actq,
477 crystalhd_hw_delete_ioqs(hw);
523 static enum BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw,
528 if (!hw || !list_id) {
533 hw->pwr_lock--;
535 tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id);
555 return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0);
558 static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts)
578 spin_lock_irqsave(&hw->lock, flags);
580 hw->tx_list_post_index = 0;
581 spin_unlock_irqrestore(&hw->lock, flags);
585 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
590 static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts)
610 spin_lock_irqsave(&hw->lock, flags);
612 hw->tx_list_post_index = 0;
613 spin_unlock_irqrestore(&hw->lock, flags);
617 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
622 static void crystalhd_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts)
627 crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0,
631 crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1,
641 err_sts = crystalhd_reg_rd(hw->adp, MISC1_TX_DMA_ERROR_STATUS);
643 if (crystalhd_tx_list0_handler(hw, err_sts))
644 crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0,
647 if (crystalhd_tx_list1_handler(hw, err_sts))
648 crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1,
651 hw->stats.tx_errors++;
837 static void crystalhd_start_tx_dma_engine(struct crystalhd_hw *hw)
841 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
844 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS,
856 static enum BC_STATUS crystalhd_stop_tx_dma_engine(struct crystalhd_hw *hw)
862 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
871 crystalhd_disable_interrupts(hw->adp);
876 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
884 l1 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0);
889 l2 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1);
900 crystalhd_enable_interrupts(hw->adp);
904 spin_lock_irqsave(&hw->lock, flags);
905 hw->tx_list_post_index = 0;
906 spin_unlock_irqrestore(&hw->lock, flags);
908 crystalhd_enable_interrupts(hw->adp);
913 static uint32_t crystalhd_get_pib_avail_cnt(struct crystalhd_hw *hw)
922 Q_addr = hw->pib_del_Q_addr;
925 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
928 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
947 static uint32_t crystalhd_get_addr_from_pib_Q(struct crystalhd_hw *hw)
952 Q_addr = hw->pib_del_Q_addr;
955 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
958 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
968 crystalhd_mem_rd(hw->adp, Q_addr + (r_offset * sizeof(uint32_t)),
978 crystalhd_mem_wr(hw->adp, Q_addr, 1, &r_offset);
983 static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel)
988 Q_addr = hw->pib_rel_Q_addr;
991 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
994 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
1009 crystalhd_mem_wr(hw->adp, Q_addr + (w_offset * sizeof(uint32_t)),
1013 crystalhd_mem_wr(hw->adp, Q_addr + sizeof(uint32_t), 1, &n_offset);
1040 static void crystalhd_hw_proc_pib(struct crystalhd_hw *hw)
1048 pib_cnt = crystalhd_get_pib_avail_cnt(hw);
1055 pib_addr = crystalhd_get_addr_from_pib_Q(hw);
1056 crystalhd_mem_rd(hw->adp, pib_addr, sizeof(struct c011_pib) / 4,
1060 rx_pkt = (struct crystalhd_rx_dma_pkt *)crystalhd_dioq_fetch(hw->rx_freeq);
1081 crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, rx_pkt->pkt_tag);
1085 crystalhd_rel_addr_to_pib_Q(hw, pib_addr);
1089 static void crystalhd_start_rx_dma_engine(struct crystalhd_hw *hw)
1093 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1096 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1099 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1102 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1108 static void crystalhd_stop_rx_dma_engine(struct crystalhd_hw *hw)
1113 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1116 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1119 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1122 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1129 l0y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0);
1132 hw->rx_list_sts[0] &= ~rx_waiting_y_intr;
1136 l1y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1);
1139 hw->rx_list_sts[1] &= ~rx_waiting_y_intr;
1143 l0uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0);
1146 hw->rx_list_sts[0] &= ~rx_waiting_uv_intr;
1150 l1uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1);
1153 hw->rx_list_sts[1] &= ~rx_waiting_uv_intr;
1159 hw->rx_list_post_index = 0;
1162 count, hw->rx_list_sts[0], hw->rx_list_sts[1]);
1165 static enum BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt)
1172 if (!hw || !rx_pkt) {
1177 if (hw->rx_list_post_index >= DMA_ENGINE_CNT) {
1178 BCMLOG_ERR("List Out Of bounds %x\n", hw->rx_list_post_index);
1182 spin_lock_irqsave(&hw->rx_lock, flags);
1183 if (sts_free != hw->rx_list_sts[hw->rx_list_post_index]) {
1184 spin_unlock_irqrestore(&hw->rx_lock, flags);
1188 if (!hw->rx_list_post_index) {
1199 rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index;
1200 hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr;
1202 hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr;
1203 hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT;
1204 spin_unlock_irqrestore(&hw->rx_lock, flags);
1206 crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag);
1208 crystalhd_start_rx_dma_engine(hw);
1211 crystalhd_reg_wr(hw->adp, y_high_addr_reg, desc_addr.high_part);
1212 crystalhd_reg_wr(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01);
1217 crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part);
1218 crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01);
1224 static enum BC_STATUS crystalhd_hw_post_cap_buff(struct crystalhd_hw *hw,
1227 enum BC_STATUS sts = crystalhd_hw_prog_rxdma(hw, rx_pkt);
1230 crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt,
1236 static void crystalhd_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index,
1249 *y_dw_dnsz = crystalhd_reg_rd(hw->adp, y_dn_sz_reg);
1250 *uv_dw_dnsz = crystalhd_reg_rd(hw->adp, uv_dn_sz_reg);
1258 static void crystalhd_hw_finalize_pause(struct crystalhd_hw *hw)
1262 hw->stop_pending = 0;
1264 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1267 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1270 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1273 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1275 hw->rx_list_post_index = 0;
1277 aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL);
1280 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
1283 static enum BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index,
1290 if (!hw || list_index >= DMA_ENGINE_CNT) {
1295 rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq,
1296 hw->rx_pkt_tag_seed + list_index);
1299 hw->rx_list_post_index, hw->rx_list_sts[0],
1300 hw->rx_list_sts[1], list_index,
1301 hw->rx_pkt_tag_seed + list_index, comp_sts);
1306 crystalhd_get_dnsz(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz);
1311 crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true,
1312 hw->rx_pkt_tag_seed + list_index);
1317 return crystalhd_hw_post_cap_buff(hw, rx_pkt);
1320 static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts,
1329 tmp_lsts = hw->rx_list_sts[0];
1334 hw->rx_list_sts[0] &= ~rx_waiting_y_intr;
1337 hw->rx_list_sts[0] &= ~rx_waiting_y_intr;
1342 hw->rx_list_sts[0] &= ~rx_y_mask;
1343 hw->rx_list_sts[0] |= rx_y_error;
1348 hw->rx_list_sts[0] &= ~rx_y_mask;
1349 hw->rx_list_sts[0] |= rx_y_error;
1350 hw->rx_list_post_index = 0;
1356 hw->rx_list_sts[0] &= ~rx_waiting_uv_intr;
1359 hw->rx_list_sts[0] &= ~rx_waiting_uv_intr;
1364 hw->rx_list_sts[0] &= ~rx_uv_mask;
1365 hw->rx_list_sts[0] |= rx_uv_error;
1370 hw->rx_list_sts[0] &= ~rx_uv_mask;
1371 hw->rx_list_sts[0] |= rx_uv_error;
1372 hw->rx_list_post_index = 0;
1377 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1382 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1385 return (tmp_lsts != hw->rx_list_sts[0]);
1388 static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, uint32_t int_sts,
1397 tmp_lsts = hw->rx_list_sts[1];
1402 hw->rx_list_sts[1] &= ~rx_waiting_y_intr;
1405 hw->rx_list_sts[1] &= ~rx_waiting_y_intr;
1411 hw->rx_list_sts[1] &= ~rx_y_mask;
1412 hw->rx_list_sts[1] |= rx_y_error;
1417 hw->rx_list_sts[1] &= ~rx_y_mask;
1418 hw->rx_list_sts[1] |= rx_y_error;
1419 hw->rx_list_post_index = 0;
1425 hw->rx_list_sts[1] &= ~rx_waiting_uv_intr;
1428 hw->rx_list_sts[1] &= ~rx_waiting_uv_intr;
1434 hw->rx_list_sts[1] &= ~rx_uv_mask;
1435 hw->rx_list_sts[1] |= rx_uv_error;
1440 hw->rx_list_sts[1] &= ~rx_uv_mask;
1441 hw->rx_list_sts[1] |= rx_uv_error;
1442 hw->rx_list_post_index = 0;
1447 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1452 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1455 return (tmp_lsts != hw->rx_list_sts[1]);
1459 static void crystalhd_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts)
1467 if (!hw) {
1475 y_err_sts = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_ERROR_STATUS);
1476 uv_err_sts = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_ERROR_STATUS);
1480 spin_lock_irqsave(&hw->rx_lock, flags);
1482 ret = crystalhd_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts);
1484 ret = crystalhd_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts);
1486 switch (hw->rx_list_sts[i]) {
1495 hw->stats.rx_errors++;
1496 crystalhd_get_dnsz(hw, i, &y_dn_sz, &uv_dn_sz);
1499 i, hw->stats.rx_errors, y_err_sts,
1501 hw->rx_list_sts[i] = sts_free;
1510 spin_unlock_irqrestore(&hw->rx_lock, flags);
1514 crystalhd_rx_pkt_done(hw, i, comp_sts);
1520 if (hw->stop_pending) {
1521 if ((hw->rx_list_sts[0] == sts_free) &&
1522 (hw->rx_list_sts[1] == sts_free))
1523 crystalhd_hw_finalize_pause(hw);
1525 crystalhd_hw_start_capture(hw);
1530 static enum BC_STATUS crystalhd_fw_cmd_post_proc(struct crystalhd_hw *hw,
1539 hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ;
1540 hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ;
1542 hw->pib_del_Q_addr, hw->pib_rel_Q_addr);
1545 if (!(crystalhd_load_firmware_config(hw->adp))) {
1556 static enum BC_STATUS crystalhd_put_ddr2sleep(struct crystalhd_hw *hw)
1562 rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, MISC_PERST_DECODER_CTRL);
1565 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1569 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1572 bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0);
1575 reg = bc_dec_reg_rd(hw->adp, SDRAM_PARAM);
1577 bc_dec_reg_wr(hw->adp, SDRAM_PARAM, reg);
1580 bc_dec_reg_wr(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1);
1583 reg = bc_dec_reg_rd(hw->adp, DecHt_PllCCtl);
1585 bc_dec_reg_wr(hw->adp, DecHt_PllCCtl, reg);
1588 bc_dec_reg_wr(hw->adp, AIO_MISC_PLL_RESET, 0x1);
1591 reg = bc_dec_reg_rd(hw->adp, DecHt_PllECtl);
1593 bc_dec_reg_wr(hw->adp, DecHt_PllECtl, reg);
1596 reg = bc_dec_reg_rd(hw->adp, DecHt_PllDCtl);
1598 bc_dec_reg_wr(hw->adp, DecHt_PllDCtl, reg);
1601 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);
1603 bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg);
1606 reg = bc_dec_reg_rd(hw->adp, DecHt_PllBCtl);
1608 bc_dec_reg_wr(hw->adp, DecHt_PllBCtl, reg);
1632 BCMLOG_ERR("Invalid hw config.. otp not programmed\n");
1709 enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw,
1722 if (!hw || !fw_cmd) {
1735 hw->pwr_lock++;
1737 hw->fwcmd_evt_sts = 0;
1738 hw->pfw_cmd_event = &fw_cmd_event;
1741 crystalhd_mem_wr(hw->adp, TS_Host2CpuSnd, FW_CMD_BUFF_SZ, cmd_buff);
1744 crystalhd_mem_rd(hw->adp, TS_Host2CpuSnd, 1, &cnt);
1747 bc_dec_reg_wr(hw->adp, Hst2CpuMbx1, TS_Host2CpuSnd);
1750 crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, 20000, rc, 0);
1767 hw->pwr_lock--;
1772 cmd_res_addr = bc_dec_reg_rd(hw->adp, Cpu2HstMbx1);
1775 crystalhd_mem_rd(hw->adp, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff);
1777 hw->pwr_lock--;
1784 sts = crystalhd_fw_cmd_post_proc(hw, fw_cmd);
1791 bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw)
1797 if (!adp || !hw->dev_started)
1800 hw->stats.num_interrupts++;
1801 hw->pwr_lock++;
1809 hw->stats.dev_interrupts++;
1816 if (hw->pfw_cmd_event) {
1817 hw->fwcmd_evt_sts = 1;
1818 crystalhd_set_event(hw->pfw_cmd_event);
1823 crystalhd_hw_proc_pib(hw);
1831 crystalhd_rx_isr(hw, intr_sts);
1834 crystalhd_tx_isr(hw, intr_sts);
1844 hw->pwr_lock--;
1849 enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp)
1851 if (!hw || !adp) {
1856 if (hw->dev_started)
1859 memset(hw, 0, sizeof(struct crystalhd_hw));
1861 hw->adp = adp;
1862 spin_lock_init(&hw->lock);
1863 spin_lock_init(&hw->rx_lock);
1864 hw->tx_ioq_tag_seed = 0x70023070;
1865 hw->rx_pkt_tag_seed = 0x70029070;
1867 hw->stop_pending = 0;
1868 crystalhd_start_device(hw->adp);
1869 hw->dev_started = true;
1872 hw->core_clock_mhz = CLOCK_PRESET;
1873 hw->prev_n = 0;
1874 hw->pwr_lock = 0;
1875 crystalhd_hw_set_core_clock(hw);
1880 enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw)
1882 if (!hw) {
1887 if (!hw->dev_started)
1891 crystalhd_hw_suspend(hw);
1892 hw->dev_started = false;
1897 enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw)
1906 if (!hw || !hw->adp) {
1911 sts = crystalhd_hw_create_ioqs(hw);
1920 mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr);
1925 crystalhd_hw_free_dma_rings(hw);
1929 hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem;
1930 hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr;
1931 hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS *
1933 hw->tx_pkt_pool[i].list_tag = 0;
1936 sts = crystalhd_dioq_add(hw->tx_freeq,
1937 &hw->tx_pkt_pool[i], false, 0);
1939 crystalhd_hw_free_dma_rings(hw);
1948 crystalhd_hw_free_dma_rings(hw);
1952 mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr);
1957 crystalhd_hw_free_dma_rings(hw);
1963 rpkt->pkt_tag = hw->rx_pkt_tag_seed + i;
1964 crystalhd_hw_free_rx_pkt(hw, rpkt);
1970 enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw)
1975 if (!hw || !hw->adp) {
1981 crystalhd_hw_delete_ioqs(hw);
1984 if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) {
1985 bc_kern_dma_free(hw->adp,
1986 hw->tx_pkt_pool[i].desc_mem.sz,
1987 hw->tx_pkt_pool[i].desc_mem.pdma_desc_start,
1988 hw->tx_pkt_pool[i].desc_mem.phy_addr);
1990 hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL;
1996 rpkt = crystalhd_hw_alloc_rx_pkt(hw);
1999 bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz,
2008 enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq,
2022 if (!hw || !ioreq || !call_back || !cb_event || !list_id) {
2034 rc = crystalhd_code_in_full(hw->adp, ioreq->uinfo.xfr_len,
2037 hw->stats.cin_busy++;
2042 tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq);
2052 add_sts = crystalhd_dioq_add(hw->tx_freeq, tx_dma_packet,
2060 hw->pwr_lock++;
2070 spin_lock_irqsave(&hw->lock, flags);
2072 if (hw->tx_list_post_index == 0) {
2080 *list_id = tx_dma_packet->list_tag = hw->tx_ioq_tag_seed +
2081 hw->tx_list_post_index;
2083 hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT;
2085 spin_unlock_irqrestore(&hw->lock, flags);
2089 crystalhd_dioq_add(hw->tx_actq, tx_dma_packet, false,
2097 crystalhd_start_tx_dma_engine(hw);
2098 crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part);
2100 crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01);
2115 enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id)
2117 if (!hw || !list_id) {
2122 crystalhd_stop_tx_dma_engine(hw);
2123 crystalhd_hw_tx_req_complete(hw, list_id, BC_STS_IO_USER_ABORT);
2128 enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
2135 if (!hw || !ioreq) {
2140 rpkt = crystalhd_hw_alloc_rx_pkt(hw);
2161 sts = crystalhd_hw_post_cap_buff(hw, rpkt);
2163 sts = crystalhd_dioq_add(hw->rx_freeq, rpkt, false, tag);
2168 enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
2177 if (!hw || !ioreq || !pib) {
2182 rpkt = crystalhd_dioq_fetch_wait(hw->rx_rdyq, timeout, &sig_pending);
2199 crystalhd_hw_free_rx_pkt(hw, rpkt);
2204 enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw)
2210 if (!hw) {
2217 rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq);
2220 sts = crystalhd_hw_post_cap_buff(hw, rx_pkt);
2229 enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw)
2233 if (!hw) {
2238 crystalhd_stop_rx_dma_engine(hw);
2241 temp = crystalhd_dioq_fetch(hw->rx_freeq);
2243 crystalhd_rx_pkt_rel_call_back(hw, temp);
2249 enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw)
2251 hw->stats.pause_cnt++;
2252 hw->stop_pending = 1;
2254 if ((hw->rx_list_sts[0] == sts_free) &&
2255 (hw->rx_list_sts[1] == sts_free))
2256 crystalhd_hw_finalize_pause(hw);
2261 enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw)
2266 hw->stop_pending = 0;
2268 aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL);
2271 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
2273 sts = crystalhd_hw_start_capture(hw);
2277 enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw)
2281 if (!hw) {
2286 sts = crystalhd_put_ddr2sleep(hw);
2292 if (!crystalhd_stop_device(hw->adp)) {
2300 void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats)
2302 if (!hw) {
2309 memset(&hw->stats, 0, sizeof(hw->stats));
2313 hw->stats.freeq_count = crystalhd_dioq_count(hw->rx_freeq);
2314 hw->stats.rdyq_count = crystalhd_dioq_count(hw->rx_rdyq);
2315 memcpy(stats, &hw->stats, sizeof(*stats));
2318 enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *hw)
2323 if (!hw) {
2328 /*n = (hw->core_clock_mhz * 3) / 20 + 1; */
2329 n = hw->core_clock_mhz/5;
2331 if (n == hw->prev_n)
2334 if (hw->pwr_lock > 0) {
2335 /* BCMLOG(BCMLOG_INFO,"pwr_lock is %u\n", hw->pwr_lock) */
2349 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);
2356 hw->core_clock_mhz, n, vco_mg);
2360 refresh_reg = (7 * hw->core_clock_mhz / 16);
2361 bc_dec_reg_wr(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | refresh_reg));
2363 bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg);
2368 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);
2371 hw->prev_n = n;