Lines Matching refs:crystalhd_reg_wr
74 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
81 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
89 crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x9D8);
99 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
104 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
108 crystalhd_reg_wr(adp, OTP_CONTENT_MISC, 0);
113 crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp);
117 crystalhd_reg_wr(adp, MISC_PERST_VREG_CTRL, 0xF3);
135 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
142 crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x10E);
151 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
156 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
168 crystalhd_reg_wr(adp, MISC3_RESET_CTRL, 1);
173 crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp);
189 crystalhd_reg_wr(adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg);
205 crystalhd_reg_wr(adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg);
216 crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg);
220 crystalhd_reg_wr(adp, MISC1_UV_RX_ERROR_STATUS, reg);
224 crystalhd_reg_wr(adp, MISC1_TX_DMA_ERROR_STATUS, reg);
232 crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts);
235 crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1);
253 crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, val);
260 crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19));
262 crystalhd_reg_wr(adp, AES_CMD, 0);
263 crystalhd_reg_wr(adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF));
264 crystalhd_reg_wr(adp, AES_CMD, 0x1);
286 crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt);
306 crystalhd_reg_wr(adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options);
312 crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, glb_cntrl);
338 crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg);
343 crystalhd_reg_wr(adp, PCIE_CLK_REQ_REG, reg);
585 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
617 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
844 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS,
876 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1096 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1102 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1116 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1122 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1211 crystalhd_reg_wr(hw->adp, y_high_addr_reg, desc_addr.high_part);
1212 crystalhd_reg_wr(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01);
1217 crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part);
1218 crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01);
1267 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1273 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1280 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
1377 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1382 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1447 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1452 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1565 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1569 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1637 crystalhd_reg_wr(adp, DCI_CMD, 0);
1639 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1656 crystalhd_reg_wr(adp, DCI_FIRMWARE_ADDR, dram_offset);
1659 crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19));
1660 crystalhd_reg_wr(adp, DCI_FIRMWARE_DATA, *temp_buff);
1672 crystalhd_reg_wr(adp, sig_reg, swapped_data);
1680 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1698 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1839 crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts);
1841 crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1);
2098 crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part);
2100 crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01);
2271 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);