Lines Matching refs:adp
32 static void crystalhd_enable_uarts(struct crystalhd_adp *adp)
34 bc_dec_reg_wr(adp, UartSelectA, BSVS_UART_STREAM);
35 bc_dec_reg_wr(adp, UartSelectB, BSVS_UART_DEC_OUTER);
39 static void crystalhd_start_dram(struct crystalhd_adp *adp)
41 bc_dec_reg_wr(adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) |
50 bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0);
51 bc_dec_reg_wr(adp, SDRAM_EXT_MODE, 2);
52 bc_dec_reg_wr(adp, SDRAM_MODE, 0x132);
53 bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0);
54 bc_dec_reg_wr(adp, SDRAM_REFRESH, 0);
55 bc_dec_reg_wr(adp, SDRAM_REFRESH, 0);
56 bc_dec_reg_wr(adp, SDRAM_MODE, 0x32);
58 bc_dec_reg_wr(adp, SDRAM_REF_PARAM, ((1 << 12) | 96));
62 static bool crystalhd_bring_out_of_rst(struct crystalhd_adp *adp)
72 rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL);
74 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
77 rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL);
81 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
89 crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x9D8);
96 rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
99 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
102 rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
104 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
108 crystalhd_reg_wr(adp, OTP_CONTENT_MISC, 0);
111 temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION);
113 crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp);
116 temp = crystalhd_reg_rd(adp, MISC_PERST_VREG_CTRL);
117 crystalhd_reg_wr(adp, MISC_PERST_VREG_CTRL, 0xF3);
122 static bool crystalhd_put_in_reset(struct crystalhd_adp *adp)
133 rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL);
135 crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg);
142 crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x10E);
148 rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL);
151 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
154 rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL);
156 crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg);
162 temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION);
168 crystalhd_reg_wr(adp, MISC3_RESET_CTRL, 1);
169 rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC3_RESET_CTRL);
173 crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp);
178 static void crystalhd_disable_interrupts(struct crystalhd_adp *adp)
181 intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG);
189 crystalhd_reg_wr(adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg);
194 static void crystalhd_enable_interrupts(struct crystalhd_adp *adp)
197 intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG);
205 crystalhd_reg_wr(adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg);
210 static void crystalhd_clear_errors(struct crystalhd_adp *adp)
214 reg = crystalhd_reg_rd(adp, MISC1_Y_RX_ERROR_STATUS);
216 crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg);
218 reg = crystalhd_reg_rd(adp, MISC1_UV_RX_ERROR_STATUS);
220 crystalhd_reg_wr(adp, MISC1_UV_RX_ERROR_STATUS, reg);
222 reg = crystalhd_reg_rd(adp, MISC1_TX_DMA_ERROR_STATUS);
224 crystalhd_reg_wr(adp, MISC1_TX_DMA_ERROR_STATUS, reg);
227 static void crystalhd_clear_interrupts(struct crystalhd_adp *adp)
229 uint32_t intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS);
232 crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts);
235 crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1);
239 static void crystalhd_soft_rst(struct crystalhd_adp *adp)
244 bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000001);
248 bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000000);
251 val = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL);
253 crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, val);
256 static bool crystalhd_load_firmware_config(struct crystalhd_adp *adp)
260 crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19));
262 crystalhd_reg_wr(adp, AES_CMD, 0);
263 crystalhd_reg_wr(adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF));
264 crystalhd_reg_wr(adp, AES_CMD, 0x1);
267 reg = crystalhd_reg_rd(adp, AES_STATUS);
277 static bool crystalhd_start_device(struct crystalhd_adp *adp)
283 reg_pwrmgmt = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL);
286 crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt);
288 if (!crystalhd_bring_out_of_rst(adp)) {
293 crystalhd_disable_interrupts(adp);
295 crystalhd_clear_errors(adp);
297 crystalhd_clear_interrupts(adp);
299 crystalhd_enable_interrupts(adp);
304 dbg_options = crystalhd_reg_rd(adp, MISC1_DMA_DEBUG_OPTIONS_REG);
306 crystalhd_reg_wr(adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options);
309 glb_cntrl = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL);
312 crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, glb_cntrl);
314 crystalhd_enable_interrupts(adp);
316 crystalhd_soft_rst(adp);
317 crystalhd_start_dram(adp);
318 crystalhd_enable_uarts(adp);
323 static bool crystalhd_stop_device(struct crystalhd_adp *adp)
329 crystalhd_disable_interrupts(adp);
330 crystalhd_clear_errors(adp);
331 crystalhd_clear_interrupts(adp);
333 if (!crystalhd_put_in_reset(adp))
336 reg = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL);
338 crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg);
341 reg = crystalhd_reg_rd(adp, PCIE_CLK_REQ_REG);
343 crystalhd_reg_wr(adp, PCIE_CLK_REQ_REG, reg);
414 crystalhd_unmap_dio(hw->adp, pkt->dio_req);
421 #define crystalhd_hw_delete_ioq(adp, q) \
423 crystalhd_delete_dioq(adp, q); \
433 crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq);
434 crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq);
435 crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq);
436 crystalhd_hw_delete_ioq(hw->adp, hw->rx_freeq);
437 crystalhd_hw_delete_ioq(hw->adp, hw->rx_rdyq);
442 sts = crystalhd_create_dioq(hw->adp, &q, cb, hw); \
483 static bool crystalhd_code_in_full(struct crystalhd_adp *adp, uint32_t needed_sz,
490 base = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Base);
491 end = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2End);
492 writep = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Wrptr);
493 readp = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Rdptr);
495 base = bc_dec_reg_rd(adp, REG_Dec_TsUser0Base);
496 end = bc_dec_reg_rd(adp, REG_Dec_TsUser0End);
497 writep = bc_dec_reg_rd(adp, REG_Dec_TsUser0Wrptr);
498 readp = bc_dec_reg_rd(adp, REG_Dec_TsUser0Rdptr);
500 base = bc_dec_reg_rd(adp, REG_DecCA_RegCinBase);
501 end = bc_dec_reg_rd(adp, REG_DecCA_RegCinEnd);
502 writep = bc_dec_reg_rd(adp, REG_DecCA_RegCinWrPtr);
503 readp = bc_dec_reg_rd(adp, REG_DecCA_RegCinRdPtr);
585 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
617 crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp);
641 err_sts = crystalhd_reg_rd(hw->adp, MISC1_TX_DMA_ERROR_STATUS);
841 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
844 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS,
862 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS);
871 crystalhd_disable_interrupts(hw->adp);
876 crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
884 l1 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0);
889 l2 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1);
900 crystalhd_enable_interrupts(hw->adp);
908 crystalhd_enable_interrupts(hw->adp);
925 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
928 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
955 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
958 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
968 crystalhd_mem_rd(hw->adp, Q_addr + (r_offset * sizeof(uint32_t)),
978 crystalhd_mem_wr(hw->adp, Q_addr, 1, &r_offset);
991 crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset);
994 crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset);
1009 crystalhd_mem_wr(hw->adp, Q_addr + (w_offset * sizeof(uint32_t)),
1013 crystalhd_mem_wr(hw->adp, Q_addr + sizeof(uint32_t), 1, &n_offset);
1056 crystalhd_mem_rd(hw->adp, pib_addr, sizeof(struct c011_pib) / 4,
1093 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1096 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1099 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1102 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1113 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1116 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1119 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1122 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1129 l0y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0);
1136 l1y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1);
1143 l0uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0);
1150 l1uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1);
1211 crystalhd_reg_wr(hw->adp, y_high_addr_reg, desc_addr.high_part);
1212 crystalhd_reg_wr(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01);
1217 crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part);
1218 crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01);
1249 *y_dw_dnsz = crystalhd_reg_rd(hw->adp, y_dn_sz_reg);
1250 *uv_dw_dnsz = crystalhd_reg_rd(hw->adp, uv_dn_sz_reg);
1264 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS);
1267 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1270 dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS);
1273 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl);
1277 aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL);
1280 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
1377 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1382 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1447 crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp);
1452 crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp);
1475 y_err_sts = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_ERROR_STATUS);
1476 uv_err_sts = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_ERROR_STATUS);
1545 if (!(crystalhd_load_firmware_config(hw->adp))) {
1562 rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, MISC_PERST_DECODER_CTRL);
1565 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1569 crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg);
1572 bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0);
1575 reg = bc_dec_reg_rd(hw->adp, SDRAM_PARAM);
1577 bc_dec_reg_wr(hw->adp, SDRAM_PARAM, reg);
1580 bc_dec_reg_wr(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1);
1583 reg = bc_dec_reg_rd(hw->adp, DecHt_PllCCtl);
1585 bc_dec_reg_wr(hw->adp, DecHt_PllCCtl, reg);
1588 bc_dec_reg_wr(hw->adp, AIO_MISC_PLL_RESET, 0x1);
1591 reg = bc_dec_reg_rd(hw->adp, DecHt_PllECtl);
1593 bc_dec_reg_wr(hw->adp, DecHt_PllECtl, reg);
1596 reg = bc_dec_reg_rd(hw->adp, DecHt_PllDCtl);
1598 bc_dec_reg_wr(hw->adp, DecHt_PllDCtl, reg);
1601 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);
1603 bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg);
1606 reg = bc_dec_reg_rd(hw->adp, DecHt_PllBCtl);
1608 bc_dec_reg_wr(hw->adp, DecHt_PllBCtl, reg);
1617 enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, uint32_t sz)
1625 if (!adp || !buffer || !sz) {
1630 reg_data = crystalhd_reg_rd(adp, OTP_CMD);
1637 crystalhd_reg_wr(adp, DCI_CMD, 0);
1639 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1646 reg_data = crystalhd_reg_rd(adp, DCI_STATUS);
1656 crystalhd_reg_wr(adp, DCI_FIRMWARE_ADDR, dram_offset);
1659 crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19));
1660 crystalhd_reg_wr(adp, DCI_FIRMWARE_DATA, *temp_buff);
1672 crystalhd_reg_wr(adp, sig_reg, swapped_data);
1680 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1684 reg_data = crystalhd_reg_rd(adp, DCI_STATUS);
1689 reg_data = crystalhd_reg_rd(adp, DCI_STATUS);
1696 reg_data = crystalhd_reg_rd(adp, DCI_CMD);
1698 crystalhd_reg_wr(adp, DCI_CMD, reg_data);
1741 crystalhd_mem_wr(hw->adp, TS_Host2CpuSnd, FW_CMD_BUFF_SZ, cmd_buff);
1744 crystalhd_mem_rd(hw->adp, TS_Host2CpuSnd, 1, &cnt);
1747 bc_dec_reg_wr(hw->adp, Hst2CpuMbx1, TS_Host2CpuSnd);
1772 cmd_res_addr = bc_dec_reg_rd(hw->adp, Cpu2HstMbx1);
1775 crystalhd_mem_rd(hw->adp, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff);
1791 bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw)
1797 if (!adp || !hw->dev_started)
1803 deco_intr = bc_dec_reg_rd(adp, Stream2Host_Intr_Sts);
1804 intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS);
1825 bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, deco_intr);
1826 bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, 0);
1839 crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts);
1841 crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1);
1849 enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp)
1851 if (!hw || !adp) {
1861 hw->adp = adp;
1868 crystalhd_start_device(hw->adp);
1906 if (!hw || !hw->adp) {
1920 mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr);
1952 mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr);
1975 if (!hw || !hw->adp) {
1985 bc_kern_dma_free(hw->adp,
1999 bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz,
2034 rc = crystalhd_code_in_full(hw->adp, ioreq->uinfo.xfr_len,
2098 crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part);
2100 crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01);
2268 aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL);
2271 crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm);
2292 if (!crystalhd_stop_device(hw->adp)) {
2349 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);
2361 bc_dec_reg_wr(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | refresh_reg));
2363 bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg);
2368 reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl);