Lines Matching refs:devpriv
294 #define devpriv ((struct pcmmio_private *)dev->private)
402 devpriv->asics[asic].num = asic;
403 devpriv->asics[asic].iobase =
409 devpriv->asics[asic].irq = 0;
410 spin_lock_init(&devpriv->asics[asic].spinlock);
416 devpriv->sprivs =
419 if (!devpriv->sprivs) {
437 s->private = devpriv->sprivs + sdev_no;
453 s->private = devpriv->sprivs + sdev_no;
474 s->private = devpriv->sprivs + sdev_no;
498 devpriv->asics[asic].iobase + port;
547 devpriv->asics[i].irq = irq[i] = 0;
551 devpriv->asics[asic].irq = irq[asic];
589 if (devpriv && devpriv->asics[i].irq)
590 free_irq(devpriv->asics[i].irq, dev);
593 if (devpriv && devpriv->sprivs)
594 kfree(devpriv->sprivs);
757 unsigned long baseaddr = devpriv->asics[asic].iobase;
794 devpriv->asics[asic].pagelock &= ~REG_PAGE_MASK;
795 devpriv->asics[asic].pagelock |= page << REG_PAGE_BITOFFSET;
798 outb(devpriv->asics[asic].pagelock,
799 devpriv->asics[asic].iobase + REG_PAGELOCK);
810 devpriv->asics[asic].pagelock |= 0x1 << port;
812 outb(devpriv->asics[asic].pagelock,
813 devpriv->asics[asic].iobase + REG_PAGELOCK);
823 devpriv->asics[asic].pagelock &= ~(0x1 << port) | REG_LOCK_MASK;
825 outb(devpriv->asics[asic].pagelock,
826 devpriv->asics[asic].iobase + REG_PAGELOCK);
836 if (irq == devpriv->asics[asic].irq) {
839 unsigned long iobase = devpriv->asics[asic].iobase;
843 spin_lock_irqsave(&devpriv->asics[asic].spinlock,
879 spin_unlock_irqrestore(&devpriv->asics[asic].spinlock,
1007 outb(0, devpriv->asics[asic].iobase + REG_ENAB0 + port);
1072 devpriv->asics[asic].iobase + REG_ENAB0 + port);
1075 devpriv->asics[asic].iobase + REG_ENAB0 + port);