Lines Matching defs:pc
20 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
22 return ssb_read32(pc->dev, offset);
26 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
28 ssb_write32(pc->dev, offset, value);
32 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
34 return ssb_read16(pc->dev, offset);
38 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
40 ssb_write16(pc->dev, offset, value);
64 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
72 if (pc->cardbusmode && (dev >= 1))
82 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
90 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
103 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
112 SSB_WARN_ON(!pc->hostmode);
115 addr = get_cfgspace_addr(pc, bus, dev, func, off);
149 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
158 SSB_WARN_ON(!pc->hostmode);
161 addr = get_cfgspace_addr(pc, bus, dev, func, off);
312 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
318 extpci_core = pc;
324 pcicore_write32(pc, SSB_PCICORE_CTL, val);
326 pcicore_write32(pc, SSB_PCICORE_CTL, val);
329 pcicore_write32(pc, SSB_PCICORE_CTL, val);
331 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
334 if (pc->dev->bus->has_cardbus_slot) {
336 pc->cardbusmode = 1;
338 ssb_gpio_out(pc->dev->bus, 1, 1);
339 ssb_gpio_outen(pc->dev->bus, 1, 1);
340 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
341 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
346 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
349 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
352 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
357 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
360 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
363 pcicore_write32(pc, SSB_PCICORE_IMASK,
377 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
379 struct ssb_bus *bus = pc->dev->bus;
402 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
411 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
414 ssb_write32(pc->dev, SSB_INTVEC, 0);
417 void ssb_pcicore_init(struct ssb_pcicore *pc)
419 struct ssb_device *dev = pc->dev;
429 pc->hostmode = pcicore_is_in_hostmode(pc);
430 if (pc->hostmode)
431 ssb_pcicore_init_hostmode(pc);
433 if (!pc->hostmode)
434 ssb_pcicore_init_clientmode(pc);
437 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
439 pcicore_write32(pc, 0x130, address);
440 return pcicore_read32(pc, 0x134);
443 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
445 pcicore_write32(pc, 0x130, address);
446 pcicore_write32(pc, 0x134, data);
449 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
459 pcicore_write32(pc, mdio_control, v);
467 pcicore_write32(pc, mdio_data, v);
471 v = pcicore_read32(pc, mdio_control);
476 pcicore_write32(pc, mdio_control, 0);
503 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
506 struct ssb_device *pdev = pc->dev;
550 if (pc->setup_done)
553 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
556 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
567 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
569 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
575 tmp = ssb_pcie_read(pc, 0x4);
577 ssb_pcie_write(pc, 0x4, tmp);
582 ssb_pcie_mdio_write(pc, serdes_rx_device,
584 ssb_pcie_mdio_write(pc, serdes_rx_device,
586 ssb_pcie_mdio_write(pc, serdes_rx_device,
590 tmp = ssb_pcie_read(pc, 0x100);
592 ssb_pcie_write(pc, 0x100, tmp);
595 pc->setup_done = 1;