Lines Matching refs:sdd
183 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
186 void __iomem *regs = sdd->regs;
204 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
217 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
232 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
236 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
237 void __iomem *regs = sdd->regs;
254 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
260 sdd->state |= TXBUSY;
264 s3c2410_dma_config(sdd->tx_dmach, 1);
265 s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
267 s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
277 sdd->state |= RXBUSY;
279 if (sci->high_speed && sdd->cur_speed >= 30000000UL
280 && !(sdd->cur_mode & SPI_CPHA))
286 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
289 s3c2410_dma_config(sdd->rx_dmach, 1);
290 s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
292 s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
300 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
305 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
306 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
308 cs = sdd->tgl_spi->controller_data;
312 sdd->tgl_spi = NULL;
319 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
322 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
323 void __iomem *regs = sdd->regs;
328 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
333 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
374 sdd->state &= ~TXBUSY;
383 sdd->state &= ~RXBUSY;
389 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
394 if (sdd->tgl_spi == spi)
395 sdd->tgl_spi = NULL;
400 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
402 void __iomem *regs = sdd->regs;
416 if (sdd->cur_mode & SPI_CPOL)
419 if (sdd->cur_mode & SPI_CPHA)
429 switch (sdd->cur_bpw) {
447 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
460 struct s3c64xx_spi_driver_data *sdd = buf_id;
463 spin_lock_irqsave(&sdd->lock, flags);
466 sdd->state &= ~RXBUSY;
468 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
471 if (!(sdd->state & TXBUSY))
472 complete(&sdd->xfer_completion);
474 spin_unlock_irqrestore(&sdd->lock, flags);
480 struct s3c64xx_spi_driver_data *sdd = buf_id;
483 spin_lock_irqsave(&sdd->lock, flags);
486 sdd->state &= ~TXBUSY;
488 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
491 if (!(sdd->state & RXBUSY))
492 complete(&sdd->xfer_completion);
494 spin_unlock_irqrestore(&sdd->lock, flags);
499 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
502 struct device *dev = &sdd->pdev->dev;
545 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
548 struct device *dev = &sdd->pdev->dev;
568 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
571 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
580 if (sdd->cur_speed != spi->max_speed_hz
581 || sdd->cur_mode != spi->mode
582 || sdd->cur_bpw != spi->bits_per_word) {
583 sdd->cur_bpw = spi->bits_per_word;
584 sdd->cur_speed = spi->max_speed_hz;
585 sdd->cur_mode = spi->mode;
586 s3c64xx_spi_config(sdd);
590 if (s3c64xx_spi_map_mssg(sdd, msg)) {
598 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
605 INIT_COMPLETION(sdd->xfer_completion);
611 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
612 sdd->cur_bpw = bpw;
613 sdd->cur_speed = speed;
614 s3c64xx_spi_config(sdd);
623 spin_lock_irqsave(&sdd->lock, flags);
626 sdd->state &= ~RXBUSY;
627 sdd->state &= ~TXBUSY;
629 enable_datapath(sdd, spi, xfer, use_dma);
632 enable_cs(sdd, spi);
635 S3C64XX_SPI_ACT(sdd);
637 spin_unlock_irqrestore(&sdd->lock, flags);
639 status = wait_for_xfer(sdd, xfer, use_dma);
642 S3C64XX_SPI_DEACT(sdd);
648 (sdd->state & RXBUSY) ? 'f' : 'p',
649 (sdd->state & TXBUSY) ? 'f' : 'p',
654 && (sdd->state & TXBUSY))
655 s3c2410_dma_ctrl(sdd->tx_dmach,
658 && (sdd->state & RXBUSY))
659 s3c2410_dma_ctrl(sdd->rx_dmach,
676 disable_cs(sdd, spi);
681 flush_fifo(sdd);
686 disable_cs(sdd, spi);
688 sdd->tgl_spi = spi;
690 s3c64xx_spi_unmap_mssg(sdd, msg);
698 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
700 if (s3c2410_dma_request(sdd->rx_dmach,
702 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
705 s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
706 s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
707 sdd->sfr_start + S3C64XX_SPI_RX_DATA);
709 if (s3c2410_dma_request(sdd->tx_dmach,
711 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
712 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
715 s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
716 s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
717 sdd->sfr_start + S3C64XX_SPI_TX_DATA);
724 struct s3c64xx_spi_driver_data *sdd = container_of(work,
729 while (!acquire_dma(sdd))
732 spin_lock_irqsave(&sdd->lock, flags);
734 while (!list_empty(&sdd->queue)
735 && !(sdd->state & SUSPND)) {
739 msg = container_of(sdd->queue.next, struct spi_message, queue);
744 sdd->state |= SPIBUSY;
746 spin_unlock_irqrestore(&sdd->lock, flags);
748 handle_msg(sdd, msg);
750 spin_lock_irqsave(&sdd->lock, flags);
752 sdd->state &= ~SPIBUSY;
755 spin_unlock_irqrestore(&sdd->lock, flags);
758 s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
759 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
765 struct s3c64xx_spi_driver_data *sdd;
768 sdd = spi_master_get_devdata(spi->master);
770 spin_lock_irqsave(&sdd->lock, flags);
772 if (sdd->state & SUSPND) {
773 spin_unlock_irqrestore(&sdd->lock, flags);
780 list_add_tail(&msg->queue, &sdd->queue);
782 queue_work(sdd->workqueue, &sdd->work);
784 spin_unlock_irqrestore(&sdd->lock, flags);
798 struct s3c64xx_spi_driver_data *sdd;
810 sdd = spi_master_get_devdata(spi->master);
811 sci = sdd->cntrlr_info;
813 spin_lock_irqsave(&sdd->lock, flags);
815 list_for_each_entry(msg, &sdd->queue, queue) {
820 spin_unlock_irqrestore(&sdd->lock, flags);
825 if (sdd->state & SUSPND) {
826 spin_unlock_irqrestore(&sdd->lock, flags);
832 spin_unlock_irqrestore(&sdd->lock, flags);
844 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); /* Max possible */
849 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
854 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
864 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
873 disable_cs(sdd, spi);
878 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
880 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
881 void __iomem *regs = sdd->regs;
884 sdd->cur_speed = 0;
886 S3C64XX_SPI_DEACT(sdd);
908 flush_fifo(sdd);
914 struct s3c64xx_spi_driver_data *sdd;
966 sdd = spi_master_get_devdata(master);
967 sdd->master = master;
968 sdd->cntrlr_info = sci;
969 sdd->pdev = pdev;
970 sdd->sfr_start = mem_res->start;
971 sdd->tx_dmach = dmatx_res->start;
972 sdd->rx_dmach = dmarx_res->start;
974 sdd->cur_bpw = 8;
991 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
992 if (sdd->regs == NULL) {
1005 sdd->clk = clk_get(&pdev->dev, "spi");
1006 if (IS_ERR(sdd->clk)) {
1008 ret = PTR_ERR(sdd->clk);
1012 if (clk_enable(sdd->clk)) {
1018 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1019 if (IS_ERR(sdd->src_clk)) {
1022 ret = PTR_ERR(sdd->src_clk);
1026 if (clk_enable(sdd->src_clk)) {
1033 sdd->workqueue = create_singlethread_workqueue(
1035 if (sdd->workqueue == NULL) {
1042 s3c64xx_spi_hwinit(sdd, pdev->id);
1044 spin_lock_init(&sdd->lock);
1045 init_completion(&sdd->xfer_completion);
1046 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1047 INIT_LIST_HEAD(&sdd->queue);
1060 sdd->rx_dmach, sdd->tx_dmach);
1065 destroy_workqueue(sdd->workqueue);
1067 clk_disable(sdd->src_clk);
1069 clk_put(sdd->src_clk);
1071 clk_disable(sdd->clk);
1073 clk_put(sdd->clk);
1076 iounmap((void *) sdd->regs);
1089 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1093 spin_lock_irqsave(&sdd->lock, flags);
1094 sdd->state |= SUSPND;
1095 spin_unlock_irqrestore(&sdd->lock, flags);
1097 while (sdd->state & SPIBUSY)
1102 destroy_workqueue(sdd->workqueue);
1104 clk_disable(sdd->src_clk);
1105 clk_put(sdd->src_clk);
1107 clk_disable(sdd->clk);
1108 clk_put(sdd->clk);
1110 iounmap((void *) sdd->regs);
1126 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1129 spin_lock_irqsave(&sdd->lock, flags);
1130 sdd->state |= SUSPND;
1131 spin_unlock_irqrestore(&sdd->lock, flags);
1133 while (sdd->state & SPIBUSY)
1137 clk_disable(sdd->src_clk);
1138 clk_disable(sdd->clk);
1140 sdd->cur_speed = 0; /* Output Clock is stopped */
1148 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1149 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1155 clk_enable(sdd->src_clk);
1156 clk_enable(sdd->clk);
1158 s3c64xx_spi_hwinit(sdd, pdev->id);
1160 spin_lock_irqsave(&sdd->lock, flags);
1161 sdd->state &= ~SUSPND;
1162 spin_unlock_irqrestore(&sdd->lock, flags);