Lines Matching refs:hw
105 struct s3c24xx_spi *hw = to_hw(spi);
112 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
113 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
118 hw->regs + S3C2410_SPCON);
119 hw->set_cs(hw->pdata, spi->chip_select, cspol);
127 struct s3c24xx_spi *hw = to_hw(spi);
162 clk = clk_get_rate(hw->clk);
182 struct s3c24xx_spi *hw = to_hw(spi);
187 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
195 struct s3c24xx_spi *hw = to_hw(spi);
216 spin_lock(&hw->bitbang.lock);
217 if (!hw->bitbang.busy) {
218 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
221 spin_unlock(&hw->bitbang.lock);
231 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
233 return hw->tx ? hw->tx[count] : 0;
274 * @hw: The hardware state.
283 void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
290 if (!hw->fiq_claimed) {
294 ret = claim_fiq(&hw->fiq_handler);
299 if (hw->tx && !hw->rx)
301 else if (hw->rx && !hw->tx)
306 regs.uregs[fiq_rspi] = (long)hw->regs;
307 regs.uregs[fiq_rrx] = (long)hw->rx;
308 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
309 regs.uregs[fiq_rcount] = hw->len - 1;
314 if (hw->fiq_mode != mode) {
317 hw->fiq_mode = mode;
336 *ack_ptr = ack_bit(hw->irq);
341 s3c24xx_set_fiq(hw->irq, true);
343 hw->fiq_mode = mode;
344 hw->fiq_inuse = 1;
358 struct s3c24xx_spi *hw = pw;
362 if (hw->fiq_inuse)
368 hw->fiq_mode = FIQ_MODE_NONE;
369 hw->fiq_claimed = 0;
371 hw->fiq_claimed = 1;
379 * @hw: The hardware state.
383 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
385 hw->fiq_handler.dev_id = hw;
386 hw->fiq_handler.name = dev_name(hw->dev);
387 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
392 * @hw: The hardware state.
397 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
399 return hw->pdata->use_fiq;
424 struct s3c24xx_spi *hw = to_hw(spi);
426 hw->tx = t->tx_buf;
427 hw->rx = t->rx_buf;
428 hw->len = t->len;
429 hw->count = 0;
431 init_completion(&hw->done);
433 hw->fiq_inuse = 0;
434 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
435 s3c24xx_spi_tryfiq(hw);
438 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
440 wait_for_completion(&hw->done);
441 return hw->count;
446 struct s3c24xx_spi *hw = dev;
447 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
448 unsigned int count = hw->count;
451 dev_dbg(hw->dev, "data-collision\n");
452 complete(&hw->done);
457 dev_dbg(hw->dev, "spi not ready for tx?\n");
458 complete(&hw->done);
462 if (!s3c24xx_spi_usingfiq(hw)) {
463 hw->count++;
465 if (hw->rx)
466 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
470 if (count < hw->len)
471 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
473 complete(&hw->done);
475 hw->count = hw->len;
476 hw->fiq_inuse = 0;
478 if (hw->rx)
479 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
481 complete(&hw->done);
488 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
492 clk_enable(hw->clk);
496 writeb(0xff, hw->regs + S3C2410_SPPRE);
497 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
498 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
500 if (hw->pdata) {
501 if (hw->set_cs == s3c24xx_spi_gpiocs)
502 gpio_direction_output(hw->pdata->pin_cs, 1);
504 if (hw->pdata->gpio_setup)
505 hw->pdata->gpio_setup(hw->pdata, 1);
512 struct s3c24xx_spi *hw;
524 hw = spi_master_get_devdata(master);
525 memset(hw, 0, sizeof(struct s3c24xx_spi));
527 hw->master = spi_master_get(master);
528 hw->pdata = pdata = pdev->dev.platform_data;
529 hw->dev = &pdev->dev;
537 platform_set_drvdata(pdev, hw);
538 init_completion(&hw->done);
542 s3c24xx_spi_initfiq(hw);
549 master->num_chipselect = hw->pdata->num_cs;
554 hw->bitbang.master = hw->master;
555 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
556 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
557 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
559 hw->master->setup = s3c24xx_spi_setup;
560 hw->master->cleanup = s3c24xx_spi_cleanup;
562 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
573 hw->ioarea = request_mem_region(res->start, resource_size(res),
576 if (hw->ioarea == NULL) {
582 hw->regs = ioremap(res->start, resource_size(res));
583 if (hw->regs == NULL) {
589 hw->irq = platform_get_irq(pdev, 0);
590 if (hw->irq < 0) {
596 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
602 hw->clk = clk_get(&pdev->dev, "spi");
603 if (IS_ERR(hw->clk)) {
605 err = PTR_ERR(hw->clk);
623 hw->set_cs = s3c24xx_spi_gpiocs;
626 hw->set_cs = pdata->set_cs;
628 s3c24xx_spi_initialsetup(hw);
632 err = spi_bitbang_start(&hw->bitbang);
641 if (hw->set_cs == s3c24xx_spi_gpiocs)
644 clk_disable(hw->clk);
645 clk_put(hw->clk);
648 free_irq(hw->irq, hw);
651 iounmap(hw->regs);
654 release_resource(hw->ioarea);
655 kfree(hw->ioarea);
659 spi_master_put(hw->master);
667 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
671 spi_unregister_master(hw->master);
673 clk_disable(hw->clk);
674 clk_put(hw->clk);
676 free_irq(hw->irq, hw);
677 iounmap(hw->regs);
679 if (hw->set_cs == s3c24xx_spi_gpiocs)
680 gpio_free(hw->pdata->pin_cs);
682 release_resource(hw->ioarea);
683 kfree(hw->ioarea);
685 spi_master_put(hw->master);
694 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
696 if (hw->pdata && hw->pdata->gpio_setup)
697 hw->pdata->gpio_setup(hw->pdata, 0);
699 clk_disable(hw->clk);
705 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
707 s3c24xx_spi_initialsetup(hw);