Lines Matching refs:dws
61 int (*write)(struct dw_spi *dws);
62 int (*read)(struct dw_spi *dws);
77 struct dw_spi *dws;
82 dws = file->private_data;
93 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
95 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
97 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
99 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
101 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
103 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
105 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
107 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
109 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
111 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
113 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
115 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
117 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
119 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
121 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
136 static int mrst_spi_debugfs_init(struct dw_spi *dws)
138 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
139 if (!dws->debugfs)
143 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
147 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
149 if (dws->debugfs)
150 debugfs_remove_recursive(dws->debugfs);
154 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
159 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
164 static void wait_till_not_busy(struct dw_spi *dws)
169 if (!(dw_readw(dws, sr) & SR_BUSY))
172 dev_err(&dws->master->dev,
176 static void flush(struct dw_spi *dws)
178 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
179 dw_readw(dws, dr);
181 wait_till_not_busy(dws);
184 static int null_writer(struct dw_spi *dws)
186 u8 n_bytes = dws->n_bytes;
188 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
189 || (dws->tx == dws->tx_end))
191 dw_writew(dws, dr, 0);
192 dws->tx += n_bytes;
194 wait_till_not_busy(dws);
198 static int null_reader(struct dw_spi *dws)
200 u8 n_bytes = dws->n_bytes;
202 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
203 && (dws->rx < dws->rx_end)) {
204 dw_readw(dws, dr);
205 dws->rx += n_bytes;
207 wait_till_not_busy(dws);
208 return dws->rx == dws->rx_end;
211 static int u8_writer(struct dw_spi *dws)
213 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
214 || (dws->tx == dws->tx_end))
217 dw_writew(dws, dr, *(u8 *)(dws->tx));
218 ++dws->tx;
220 wait_till_not_busy(dws);
224 static int u8_reader(struct dw_spi *dws)
226 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
227 && (dws->rx < dws->rx_end)) {
228 *(u8 *)(dws->rx) = dw_readw(dws, dr);
229 ++dws->rx;
232 wait_till_not_busy(dws);
233 return dws->rx == dws->rx_end;
236 static int u16_writer(struct dw_spi *dws)
238 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
239 || (dws->tx == dws->tx_end))
242 dw_writew(dws, dr, *(u16 *)(dws->tx));
243 dws->tx += 2;
245 wait_till_not_busy(dws);
249 static int u16_reader(struct dw_spi *dws)
253 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
254 && (dws->rx < dws->rx_end)) {
255 temp = dw_readw(dws, dr);
256 *(u16 *)(dws->rx) = temp;
257 dws->rx += 2;
260 wait_till_not_busy(dws);
261 return dws->rx == dws->rx_end;
264 static void *next_transfer(struct dw_spi *dws)
266 struct spi_message *msg = dws->cur_msg;
267 struct spi_transfer *trans = dws->cur_transfer;
271 dws->cur_transfer =
285 static int map_dma_buffers(struct dw_spi *dws)
287 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
288 || !dws->cur_chip->enable_dma)
291 if (dws->cur_transfer->tx_dma)
292 dws->tx_dma = dws->cur_transfer->tx_dma;
294 if (dws->cur_transfer->rx_dma)
295 dws->rx_dma = dws->cur_transfer->rx_dma;
301 static void giveback(struct dw_spi *dws)
307 spin_lock_irqsave(&dws->lock, flags);
308 msg = dws->cur_msg;
309 dws->cur_msg = NULL;
310 dws->cur_transfer = NULL;
311 dws->prev_chip = dws->cur_chip;
312 dws->cur_chip = NULL;
313 dws->dma_mapped = 0;
314 queue_work(dws->workqueue, &dws->pump_messages);
315 spin_unlock_irqrestore(&dws->lock, flags);
321 if (!last_transfer->cs_change && dws->cs_control)
322 dws->cs_control(MRST_SPI_DEASSERT);
329 static void int_error_stop(struct dw_spi *dws, const char *msg)
332 flush(dws);
333 spi_enable_chip(dws, 0);
335 dev_err(&dws->master->dev, "%s\n", msg);
336 dws->cur_msg->state = ERROR_STATE;
337 tasklet_schedule(&dws->pump_transfers);
340 static void transfer_complete(struct dw_spi *dws)
343 dws->cur_msg->actual_length += dws->len;
346 dws->cur_msg->state = next_transfer(dws);
349 if (dws->cur_msg->state == DONE_STATE) {
350 dws->cur_msg->status = 0;
351 giveback(dws);
353 tasklet_schedule(&dws->pump_transfers);
356 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
359 u32 int_level = dws->fifo_len / 2;
362 irq_status = dw_readw(dws, isr) & irq_mask;
365 dw_readw(dws, txoicr);
366 dw_readw(dws, rxoicr);
367 dw_readw(dws, rxuicr);
368 int_error_stop(dws, "interrupt_transfer: fifo overrun");
373 spi_mask_intr(dws, SPI_INT_TXEI);
375 left = (dws->tx_end - dws->tx) / dws->n_bytes;
379 dws->write(dws);
380 dws->read(dws);
383 if (dws->tx_end > dws->tx)
384 spi_umask_intr(dws, SPI_INT_TXEI);
386 transfer_complete(dws);
394 struct dw_spi *dws = dev_id;
397 irq_status = dw_readw(dws, isr) & irq_mask;
401 if (!dws->cur_msg) {
402 spi_mask_intr(dws, SPI_INT_TXEI);
407 return dws->transfer_handler(dws);
411 static void poll_transfer(struct dw_spi *dws)
413 while (dws->write(dws))
414 dws->read(dws);
416 transfer_complete(dws);
419 static void dma_transfer(struct dw_spi *dws, int cs_change)
425 struct dw_spi *dws = (struct dw_spi *)data;
440 message = dws->cur_msg;
441 transfer = dws->cur_transfer;
442 chip = dws->cur_chip;
446 chip->clk_div = dws->max_freq / chip->speed_hz;
468 dws->n_bytes = chip->n_bytes;
469 dws->dma_width = chip->dma_width;
470 dws->cs_control = chip->cs_control;
472 dws->rx_dma = transfer->rx_dma;
473 dws->tx_dma = transfer->tx_dma;
474 dws->tx = (void *)transfer->tx_buf;
475 dws->tx_end = dws->tx + transfer->len;
476 dws->rx = transfer->rx_buf;
477 dws->rx_end = dws->rx + transfer->len;
478 dws->write = dws->tx ? chip->write : null_writer;
479 dws->read = dws->rx ? chip->read : null_reader;
480 dws->cs_change = transfer->cs_change;
481 dws->len = dws->cur_transfer->len;
482 if (chip != dws->prev_chip)
493 if (speed > dws->max_freq) {
501 clk_div = dws->max_freq / speed;
513 dws->n_bytes = 1;
514 dws->dma_width = 1;
515 dws->read = (dws->read != null_reader) ?
517 dws->write = (dws->write != null_writer) ?
521 dws->n_bytes = 2;
522 dws->dma_width = 2;
523 dws->read = (dws->read != null_reader) ?
525 dws->write = (dws->write != null_writer) ?
546 if (dws->cs_control) {
547 if (dws->rx && dws->tx)
549 else if (dws->rx)
559 dws->dma_mapped = map_dma_buffers(dws);
565 if (!dws->dma_mapped && !chip->poll_mode) {
566 int templen = dws->len / dws->n_bytes;
567 txint_level = dws->fifo_len / 2;
571 dws->transfer_handler = interrupt_transfer;
580 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
581 spi_enable_chip(dws, 0);
583 if (dw_readw(dws, ctrl0) != cr0)
584 dw_writew(dws, ctrl0, cr0);
586 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
587 spi_chip_sel(dws, spi->chip_select);
590 spi_mask_intr(dws, 0xff);
592 spi_umask_intr(dws, imask);
594 dw_writew(dws, txfltr, txint_level);
596 spi_enable_chip(dws, 1);
598 dws->prev_chip = chip;
601 if (dws->dma_mapped)
602 dma_transfer(dws, cs_change);
605 poll_transfer(dws);
610 giveback(dws);
616 struct dw_spi *dws =
621 spin_lock_irqsave(&dws->lock, flags);
622 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
623 dws->busy = 0;
624 spin_unlock_irqrestore(&dws->lock, flags);
629 if (dws->cur_msg) {
630 spin_unlock_irqrestore(&dws->lock, flags);
635 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
636 list_del_init(&dws->cur_msg->queue);
639 dws->cur_msg->state = START_STATE;
640 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
643 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
646 tasklet_schedule(&dws->pump_transfers);
648 dws->busy = 1;
649 spin_unlock_irqrestore(&dws->lock, flags);
655 struct dw_spi *dws = spi_master_get_devdata(spi->master);
658 spin_lock_irqsave(&dws->lock, flags);
660 if (dws->run == QUEUE_STOPPED) {
661 spin_unlock_irqrestore(&dws->lock, flags);
669 list_add_tail(&msg->queue, &dws->queue);
671 if (dws->run == QUEUE_RUNNING && !dws->busy) {
673 if (dws->cur_transfer || dws->cur_msg)
674 queue_work(dws->workqueue,
675 &dws->pump_messages);
678 spin_unlock_irqrestore(&dws->lock, flags);
679 pump_messages(&dws->pump_messages);
684 spin_unlock_irqrestore(&dws->lock, flags);
765 static int __devinit init_queue(struct dw_spi *dws)
767 INIT_LIST_HEAD(&dws->queue);
768 spin_lock_init(&dws->lock);
770 dws->run = QUEUE_STOPPED;
771 dws->busy = 0;
773 tasklet_init(&dws->pump_transfers,
774 pump_transfers, (unsigned long)dws);
776 INIT_WORK(&dws->pump_messages, pump_messages);
777 dws->workqueue = create_singlethread_workqueue(
778 dev_name(dws->master->dev.parent));
779 if (dws->workqueue == NULL)
785 static int start_queue(struct dw_spi *dws)
789 spin_lock_irqsave(&dws->lock, flags);
791 if (dws->run == QUEUE_RUNNING || dws->busy) {
792 spin_unlock_irqrestore(&dws->lock, flags);
796 dws->run = QUEUE_RUNNING;
797 dws->cur_msg = NULL;
798 dws->cur_transfer = NULL;
799 dws->cur_chip = NULL;
800 dws->prev_chip = NULL;
801 spin_unlock_irqrestore(&dws->lock, flags);
803 queue_work(dws->workqueue, &dws->pump_messages);
808 static int stop_queue(struct dw_spi *dws)
814 spin_lock_irqsave(&dws->lock, flags);
815 dws->run = QUEUE_STOPPED;
816 while (!list_empty(&dws->queue) && dws->busy && limit--) {
817 spin_unlock_irqrestore(&dws->lock, flags);
819 spin_lock_irqsave(&dws->lock, flags);
822 if (!list_empty(&dws->queue) || dws->busy)
824 spin_unlock_irqrestore(&dws->lock, flags);
829 static int destroy_queue(struct dw_spi *dws)
833 status = stop_queue(dws);
836 destroy_workqueue(dws->workqueue);
841 static void spi_hw_init(struct dw_spi *dws)
843 spi_enable_chip(dws, 0);
844 spi_mask_intr(dws, 0xff);
845 spi_enable_chip(dws, 1);
846 flush(dws);
852 if (!dws->fifo_len) {
855 dw_writew(dws, txfltr, fifo);
856 if (fifo != dw_readw(dws, txfltr))
860 dws->fifo_len = (fifo == 257) ? 0 : fifo;
861 dw_writew(dws, txfltr, 0);
865 int __devinit dw_spi_add_host(struct dw_spi *dws)
870 BUG_ON(dws == NULL);
872 master = spi_alloc_master(dws->parent_dev, 0);
878 dws->master = master;
879 dws->type = SSI_MOTO_SPI;
880 dws->prev_chip = NULL;
881 dws->dma_inited = 0;
882 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
884 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
885 "dw_spi", dws);
892 master->bus_num = dws->bus_num;
893 master->num_chipselect = dws->num_cs;
898 dws->dma_inited = 0;
901 spi_hw_init(dws);
904 ret = init_queue(dws);
909 ret = start_queue(dws);
915 spi_master_set_devdata(master, dws);
922 mrst_spi_debugfs_init(dws);
926 destroy_queue(dws);
928 spi_enable_chip(dws, 0);
929 free_irq(dws->irq, dws);
937 void __devexit dw_spi_remove_host(struct dw_spi *dws)
941 if (!dws)
943 mrst_spi_debugfs_remove(dws);
946 status = destroy_queue(dws);
948 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
951 spi_enable_chip(dws, 0);
953 spi_set_clk(dws, 0);
954 free_irq(dws->irq, dws);
957 spi_unregister_master(dws->master);
961 int dw_spi_suspend_host(struct dw_spi *dws)
965 ret = stop_queue(dws);
968 spi_enable_chip(dws, 0);
969 spi_set_clk(dws, 0);
974 int dw_spi_resume_host(struct dw_spi *dws)
978 spi_hw_init(dws);
979 ret = start_queue(dws);
981 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);