Lines Matching refs:davinci_spi_dma
150 struct davinci_spi_dma {
177 struct davinci_spi_dma *dma_channels;
359 struct davinci_spi_dma *davinci_spi_dma;
363 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
367 edma_stop(davinci_spi_dma->dma_rx_channel);
369 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
371 complete(&davinci_spi_dma->dma_rx_completion);
380 struct davinci_spi_dma *davinci_spi_dma;
384 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
388 edma_stop(davinci_spi_dma->dma_tx_channel);
390 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
392 complete(&davinci_spi_dma->dma_tx_completion);
400 struct davinci_spi_dma *davinci_spi_dma;
406 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
410 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
412 davinci_spi_dma->eventq);
417 davinci_spi_dma->dma_rx_channel = r;
418 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
420 davinci_spi_dma->eventq);
422 edma_free_channel(davinci_spi_dma->dma_rx_channel);
423 davinci_spi_dma->dma_rx_channel = -1;
427 davinci_spi_dma->dma_tx_channel = r;
443 struct davinci_spi_dma *davinci_spi_dma;
456 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
458 if ((davinci_spi_dma->dma_rx_channel == -1)
459 || (davinci_spi_dma->dma_tx_channel == -1)) {
571 struct davinci_spi_dma *davinci_spi_dma;
573 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
576 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
578 if ((davinci_spi_dma->dma_rx_channel != -1)
579 && (davinci_spi_dma->dma_tx_channel != -1)) {
580 edma_free_channel(davinci_spi_dma->dma_tx_channel);
581 edma_free_channel(davinci_spi_dma->dma_rx_channel);
815 struct davinci_spi_dma *davinci_spi_dma;
825 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
839 init_completion(&davinci_spi_dma->dma_rx_completion);
840 init_completion(&davinci_spi_dma->dma_tx_completion);
907 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
909 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
910 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
911 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
912 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
928 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
930 edma_set_src(davinci_spi_dma->dma_rx_channel,
932 edma_set_dest(davinci_spi_dma->dma_rx_channel,
934 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
935 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
940 edma_start(davinci_spi_dma->dma_tx_channel);
943 edma_start(davinci_spi_dma->dma_rx_channel);
950 &davinci_spi_dma->dma_tx_completion);
954 &davinci_spi_dma->dma_rx_completion);
1136 * sizeof(struct davinci_spi_dma), GFP_KERNEL);