Lines Matching defs:davinci_spi
162 struct davinci_spi {
180 void (*get_rx)(u32 rx_data, struct davinci_spi *);
181 u32 (*get_tx)(struct davinci_spi *);
188 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
190 u8 *rx = davinci_spi->rx;
193 davinci_spi->rx = rx;
196 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
198 u16 *rx = davinci_spi->rx;
201 davinci_spi->rx = rx;
204 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
207 const u8 *tx = davinci_spi->tx;
210 davinci_spi->tx = tx;
214 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
217 const u16 *tx = davinci_spi->tx;
220 davinci_spi->tx = tx;
252 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
255 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
257 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
265 struct davinci_spi *davinci_spi;
269 davinci_spi = spi_master_get_devdata(spi->master);
270 pdata = davinci_spi->pdata;
277 set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
280 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
282 while ((ioread32(davinci_spi->base + SPIBUF)
301 struct davinci_spi *davinci_spi;
306 davinci_spi = spi_master_get_devdata(spi->master);
307 pdata = davinci_spi->pdata;
323 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
324 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
325 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
327 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
328 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
329 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
336 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
341 clkspeed = clk_get_rate(davinci_spi->clk);
349 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
350 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
358 struct davinci_spi *davinci_spi;
362 davinci_spi = spi_master_get_devdata(spi->master);
363 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
364 pdata = davinci_spi->pdata;
379 struct davinci_spi *davinci_spi;
383 davinci_spi = spi_master_get_devdata(spi->master);
384 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
385 pdata = davinci_spi->pdata;
399 struct davinci_spi *davinci_spi;
405 davinci_spi = spi_master_get_devdata(spi->master);
406 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
407 pdata = davinci_spi->pdata;
408 sdev = davinci_spi->bitbang.master->dev.parent;
442 struct davinci_spi *davinci_spi;
446 davinci_spi = spi_master_get_devdata(spi->master);
447 sdev = davinci_spi->bitbang.master->dev.parent;
453 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
455 if (use_dma && davinci_spi->dma_channels) {
456 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
484 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
487 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
491 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
494 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
498 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
501 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
517 if (davinci_spi->version == SPI_VERSION_2) {
518 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
520 set_fmt_bits(davinci_spi->base,
521 (davinci_spi->pdata->wdelay
526 if (davinci_spi->pdata->odd_parity)
527 set_fmt_bits(davinci_spi->base,
531 clear_fmt_bits(davinci_spi->base,
535 if (davinci_spi->pdata->parity_enable)
536 set_fmt_bits(davinci_spi->base,
540 clear_fmt_bits(davinci_spi->base,
544 if (davinci_spi->pdata->wait_enable)
545 set_fmt_bits(davinci_spi->base,
549 clear_fmt_bits(davinci_spi->base,
553 if (davinci_spi->pdata->timer_disable)
554 set_fmt_bits(davinci_spi->base,
558 clear_fmt_bits(davinci_spi->base,
570 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
573 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
575 if (use_dma && davinci_spi->dma_channels) {
576 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
587 struct davinci_spi *davinci_spi)
606 iowrite32(op_mode, davinci_spi->base + SPIPC0);
609 set_io_bits(davinci_spi->base + SPIGCR1,
612 clear_io_bits(davinci_spi->base + SPIGCR1,
618 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
621 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
636 if (davinci_spi->version == SPI_VERSION_2) {
673 struct davinci_spi *davinci_spi;
680 davinci_spi = spi_master_get_devdata(spi->master);
681 pdata = davinci_spi->pdata;
683 davinci_spi->tx = t->tx_buf;
684 davinci_spi->rx = t->rx_buf;
687 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
688 davinci_spi->count = t->len / conv;
690 INIT_COMPLETION(davinci_spi->done);
692 ret = davinci_spi_bufs_prep(spi, davinci_spi);
697 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
701 davinci_spi->base + SPIDELAY);
703 count = davinci_spi->count;
707 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
711 while ((ioread32(davinci_spi->base + SPIBUF)
717 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
720 tx_data = davinci_spi->get_tx(davinci_spi);
725 buf_val = ioread32(davinci_spi->base + SPIBUF);
728 davinci_spi->base + SPIDAT1);
732 while (ioread32(davinci_spi->base + SPIBUF)
738 buf_val = ioread32(davinci_spi->base + SPIBUF);
739 davinci_spi->get_rx(buf_val, davinci_spi);
748 if ((ioread32(davinci_spi->base + SPIBUF)
751 davinci_spi->base + SPIDAT1);
753 while (ioread32(davinci_spi->base + SPIBUF) &
757 flg_val = ioread32(davinci_spi->base + SPIFLG);
758 buf_val = ioread32(davinci_spi->base + SPIBUF);
760 davinci_spi->get_rx(buf_val, davinci_spi);
769 for (i = 0; i < davinci_spi->count; i++) {
770 set_io_bits(davinci_spi->base + SPIINT,
776 davinci_spi->base + SPIDAT1);
778 while (ioread32(davinci_spi->base + SPIINT) &
783 davinci_spi->base + SPIDAT1);
791 int_status = ioread32(davinci_spi->base + SPIFLG);
793 ret = davinci_spi_check_error(davinci_spi, int_status);
798 davinci_spi->count *= conv;
809 struct davinci_spi *davinci_spi;
821 davinci_spi = spi_master_get_devdata(spi->master);
822 pdata = davinci_spi->pdata;
823 sdev = davinci_spi->bitbang.master->dev.parent;
825 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
827 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
828 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
830 davinci_spi->tx = t->tx_buf;
831 davinci_spi->rx = t->rx_buf;
834 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
835 davinci_spi->count = t->len / conv;
837 INIT_COMPLETION(davinci_spi->done);
853 ret = davinci_spi_bufs_prep(spi, davinci_spi);
860 davinci_spi->base + SPIDELAY);
862 count = davinci_spi->count; /* the number of elements */
868 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
873 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
875 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
876 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
878 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
880 while ((ioread32(davinci_spi->base + SPIBUF)
897 (void *)davinci_spi->tmp_buf, count + 1,
916 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
965 int_status = ioread32(davinci_spi->base + SPIFLG);
967 ret = davinci_spi_check_error(davinci_spi, int_status);
972 davinci_spi->count *= conv;
980 * @context_data: structure for SPI Master controller davinci_spi
984 struct davinci_spi *davinci_spi = context_data;
988 int_status = ioread32(davinci_spi->base + SPIFLG);
994 rx_data = ioread32(davinci_spi->base + SPIBUF);
995 davinci_spi->get_rx(rx_data, davinci_spi);
999 davinci_spi->base + SPIINT);
1001 (void)davinci_spi_check_error(davinci_spi, int_status);
1003 int_status = ioread32(davinci_spi->base + SPIFLG);
1016 struct davinci_spi *davinci_spi;
1030 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
1038 davinci_spi = spi_master_get_devdata(master);
1039 if (davinci_spi == NULL) {
1050 davinci_spi->pbase = r->start;
1051 davinci_spi->region_size = resource_size(r);
1052 davinci_spi->pdata = pdata;
1054 mem = request_mem_region(r->start, davinci_spi->region_size,
1061 davinci_spi->base = (struct davinci_spi_reg __iomem *)
1062 ioremap(r->start, davinci_spi->region_size);
1063 if (davinci_spi->base == NULL) {
1068 davinci_spi->irq = platform_get_irq(pdev, 0);
1069 if (davinci_spi->irq <= 0) {
1074 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1075 dev_name(&pdev->dev), davinci_spi);
1080 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1081 if (davinci_spi->tmp_buf == NULL) {
1086 davinci_spi->bitbang.master = spi_master_get(master);
1087 if (davinci_spi->bitbang.master == NULL) {
1092 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1093 if (IS_ERR(davinci_spi->clk)) {
1097 clk_enable(davinci_spi->clk);
1105 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1106 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1108 davinci_spi->version = pdata->version;
1111 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1112 if (davinci_spi->version == SPI_VERSION_2)
1113 davinci_spi->bitbang.flags |= SPI_READY;
1131 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1134 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1135 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1137 if (davinci_spi->dma_channels == NULL) {
1143 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1144 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1146 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1147 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1149 davinci_spi->dma_channels[i].eventq = dma_eventq;
1157 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1158 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1160 init_completion(&davinci_spi->done);
1163 iowrite32(0, davinci_spi->base + SPIGCR0);
1165 iowrite32(1, davinci_spi->base + SPIGCR0);
1168 if (davinci_spi->pdata->clk_internal)
1169 set_io_bits(davinci_spi->base + SPIGCR1,
1172 clear_io_bits(davinci_spi->base + SPIGCR1,
1176 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1178 if (davinci_spi->pdata->intr_level)
1179 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1181 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1183 ret = spi_bitbang_start(&davinci_spi->bitbang);
1187 dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
1191 " using IRQ %d\n", davinci_spi->irq);
1196 clk_disable(davinci_spi->clk);
1197 clk_put(davinci_spi->clk);
1201 kfree(davinci_spi->tmp_buf);
1203 free_irq(davinci_spi->irq, davinci_spi);
1205 iounmap(davinci_spi->base);
1207 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1225 struct davinci_spi *davinci_spi;
1229 davinci_spi = spi_master_get_devdata(master);
1231 spi_bitbang_stop(&davinci_spi->bitbang);
1233 clk_disable(davinci_spi->clk);
1234 clk_put(davinci_spi->clk);
1236 kfree(davinci_spi->tmp_buf);
1237 free_irq(davinci_spi->irq, davinci_spi);
1238 iounmap(davinci_spi->base);
1239 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);