Lines Matching refs:div
119 u32 div, brg;
121 for (div = 0; div < 4; div++) {
122 brg = mainclk_hz / speed_hz / (4 << div);
126 break; /* set lowest brg (div is == 0) */
129 break; /* we have valid brg and div */
131 if (div == 4) {
132 div = 3; /* speed_hz too small */
133 brg = (63 + 1); /* set highest brg and div */
136 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
744 /* use minimal allowed brg and div values as initial setting: */
916 * produce valid brg and div