Lines Matching refs:chip_info
1242 struct pl022_config_chip *chip_info)
1244 if ((chip_info->lbm != LOOPBACK_ENABLED)
1245 && (chip_info->lbm != LOOPBACK_DISABLED)) {
1246 dev_err(chip_info->dev,
1250 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1251 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1252 dev_err(chip_info->dev,
1256 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1258 dev_err(chip_info->dev,
1263 if ((chip_info->hierarchy != SSP_MASTER)
1264 && (chip_info->hierarchy != SSP_SLAVE)) {
1265 dev_err(chip_info->dev,
1269 if (((chip_info->clk_freq).cpsdvsr < CPSDVR_MIN)
1270 || ((chip_info->clk_freq).cpsdvsr > CPSDVR_MAX)) {
1271 dev_err(chip_info->dev,
1275 if ((chip_info->endian_rx != SSP_RX_MSB)
1276 && (chip_info->endian_rx != SSP_RX_LSB)) {
1277 dev_err(chip_info->dev,
1281 if ((chip_info->endian_tx != SSP_TX_MSB)
1282 && (chip_info->endian_tx != SSP_TX_LSB)) {
1283 dev_err(chip_info->dev,
1287 if ((chip_info->data_size < SSP_DATA_BITS_4)
1288 || (chip_info->data_size > SSP_DATA_BITS_32)) {
1289 dev_err(chip_info->dev,
1293 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1294 && (chip_info->com_mode != DMA_TRANSFER)
1295 && (chip_info->com_mode != POLLING_TRANSFER)) {
1296 dev_err(chip_info->dev,
1300 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1301 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
1302 dev_err(chip_info->dev,
1306 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1307 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
1308 dev_err(chip_info->dev,
1312 if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) {
1313 if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE)
1314 && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) {
1315 dev_err(chip_info->dev,
1319 if ((chip_info->clk_pol != SSP_CLK_POL_IDLE_LOW)
1320 && (chip_info->clk_pol != SSP_CLK_POL_IDLE_HIGH)) {
1321 dev_err(chip_info->dev,
1326 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1327 if ((chip_info->ctrl_len < SSP_BITS_4)
1328 || (chip_info->ctrl_len > SSP_BITS_32)) {
1329 dev_err(chip_info->dev,
1333 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1334 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1335 dev_err(chip_info->dev,
1341 if ((chip_info->duplex !=
1343 && (chip_info->duplex !=
1345 dev_err(chip_info->dev,
1349 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1350 dev_err(chip_info->dev,
1357 if (chip_info->cs_control == NULL) {
1358 dev_warn(chip_info->dev,
1360 chip_info->cs_control = null_cs_control;
1464 * @chip_info: chip info provided by client device
1470 static int process_dma_info(struct pl022_config_chip *chip_info,
1473 dev_err(chip_info->dev,
1496 struct pl022_config_chip *chip_info;
1525 chip_info = spi->controller_data;
1527 if (chip_info == NULL) {
1532 chip_info =
1535 if (!chip_info) {
1545 chip_info->dev = &spi->dev;
1550 chip_info->lbm = LOOPBACK_DISABLED;
1551 chip_info->com_mode = POLLING_TRANSFER;
1552 chip_info->iface = SSP_INTERFACE_MOTOROLA_SPI;
1553 chip_info->hierarchy = SSP_SLAVE;
1554 chip_info->slave_tx_disable = DO_NOT_DRIVE_TX;
1555 chip_info->endian_tx = SSP_TX_LSB;
1556 chip_info->endian_rx = SSP_RX_LSB;
1557 chip_info->data_size = SSP_DATA_BITS_12;
1558 chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM;
1559 chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC;
1560 chip_info->clk_phase = SSP_CLK_SECOND_EDGE;
1561 chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW;
1562 chip_info->ctrl_len = SSP_BITS_8;
1563 chip_info->wait_state = SSP_MWIRE_WAIT_ZERO;
1564 chip_info->duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX;
1565 chip_info->cs_control = null_cs_control;
1575 if ((0 == chip_info->clk_freq.cpsdvsr)
1576 && (0 == chip_info->clk_freq.scr)) {
1579 &chip_info->clk_freq);
1583 if ((chip_info->clk_freq.cpsdvsr % 2) != 0)
1584 chip_info->clk_freq.cpsdvsr =
1585 chip_info->clk_freq.cpsdvsr - 1;
1587 status = verify_controller_parameters(pl022, chip_info);
1593 chip->xfer_type = chip_info->com_mode;
1594 chip->cs_control = chip_info->cs_control;
1596 if (chip_info->data_size <= 8) {
1601 } else if (chip_info->data_size <= 16) {
1627 if ((chip_info->com_mode == DMA_TRANSFER)
1631 status = process_dma_info(chip_info, chip);
1647 chip->cpsr = chip_info->clk_freq.cpsdvsr;
1653 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1657 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1659 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1661 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1663 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1666 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1668 SSP_WRITE_BITS(chip->cr1, chip_info->endian_rx,
1670 SSP_WRITE_BITS(chip->cr1, chip_info->endian_tx,
1672 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1674 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1677 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1679 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1683 SSP_WRITE_BITS(chip->cr0, chip_info->clk_pol, SSP_CR0_MASK_SPO, 6);
1684 SSP_WRITE_BITS(chip->cr0, chip_info->clk_phase, SSP_CR0_MASK_SPH, 7);
1685 SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1688 SSP_WRITE_BITS(chip->cr1, chip_info->lbm, SSP_CR1_MASK_LBM, 0);
1690 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1691 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);