Lines Matching defs:virtbase
337 * @virtbase: The virtual memory where the SSP is mapped
361 void __iomem *virtbase;
517 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
518 readw(SSP_DR(pl022->virtbase));
519 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
535 writel(chip->cr0, SSP_CR0(pl022->virtbase));
537 writew(chip->cr0, SSP_CR0(pl022->virtbase));
538 writew(chip->cr1, SSP_CR1(pl022->virtbase));
539 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
540 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
541 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
542 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
623 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
624 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
626 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
627 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
629 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
630 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
632 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
633 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
634 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
635 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
660 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
664 readw(SSP_DR(pl022->virtbase));
668 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
672 (u16) readw(SSP_DR(pl022->virtbase));
676 readl(SSP_DR(pl022->virtbase));
689 writew(0x0, SSP_DR(pl022->virtbase));
692 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
695 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
698 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
709 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
713 readw(SSP_DR(pl022->virtbase));
717 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
721 (u16) readw(SSP_DR(pl022->virtbase));
725 readl(SSP_DR(pl022->virtbase));
788 irq_status = readw(SSP_MIS(pl022->virtbase));
801 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
804 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
814 SSP_IMSC(pl022->virtbase));
815 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
816 writew((readw(SSP_CR1(pl022->virtbase)) &
817 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
830 writew(readw(SSP_IMSC(pl022->virtbase)) &
832 SSP_IMSC(pl022->virtbase));
842 SSP_IMSC(pl022->virtbase));
843 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
949 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
992 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
993 SSP_CR1(pl022->virtbase));
1019 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1020 SSP_CR1(pl022->virtbase));
1021 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1064 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1065 SSP_CR1(pl022->virtbase));
1765 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
1766 if (pl022->virtbase == NULL) {
1771 adev->res.start, pl022->virtbase);
1781 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
1782 SSP_CR1(pl022->virtbase));
1823 iounmap(pl022->virtbase);
1852 iounmap(pl022->virtbase);