Lines Matching refs:curregs
79 unsigned char curregs[NUM_ZSREGS];
277 __load_zsregs(channel, up->curregs);
291 up->curregs[R12] = (brg & 0xff);
292 up->curregs[R13] = (brg >> 8) & 0xff;
486 __load_zsregs(channel, up->curregs);
669 up->curregs[R5] |= set_bits;
670 up->curregs[R5] &= ~clear_bits;
671 write_zsreg(channel, R5, up->curregs[R5]);
736 up->curregs[R1] &= ~RxINT_MASK;
747 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
748 if (new_reg != up->curregs[R15]) {
749 up->curregs[R15] = new_reg;
752 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
773 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
774 if (new_reg != up->curregs[R5]) {
775 up->curregs[R5] = new_reg;
778 write_zsreg(channel, R5, up->curregs[R5]);
792 up->curregs[R3] |= RxENAB;
793 up->curregs[R5] |= TxENAB;
795 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
852 up->curregs[R3] &= ~RxENAB;
853 up->curregs[R5] &= ~TxENAB;
856 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
857 up->curregs[R5] &= ~SND_BRK;
871 up->curregs[R10] = NRZ;
872 up->curregs[R11] = TCBR | RCBR;
875 up->curregs[R4] &= ~XCLK_MASK;
876 up->curregs[R4] |= X16CLK;
877 up->curregs[R12] = brg & 0xff;
878 up->curregs[R13] = (brg >> 8) & 0xff;
879 up->curregs[R14] = BRSRC | BRENAB;
882 up->curregs[R3] &= ~RxN_MASK;
883 up->curregs[R5] &= ~TxN_MASK;
886 up->curregs[R3] |= Rx5;
887 up->curregs[R5] |= Tx5;
891 up->curregs[R3] |= Rx6;
892 up->curregs[R5] |= Tx6;
896 up->curregs[R3] |= Rx7;
897 up->curregs[R5] |= Tx7;
902 up->curregs[R3] |= Rx8;
903 up->curregs[R5] |= Tx8;
907 up->curregs[R4] &= ~0x0c;
909 up->curregs[R4] |= SB2;
911 up->curregs[R4] |= SB1;
913 up->curregs[R4] |= PAR_ENAB;
915 up->curregs[R4] &= ~PAR_ENAB;
917 up->curregs[R4] |= PAR_EVEN;
919 up->curregs[R4] &= ~PAR_EVEN;
1254 up->curregs[R15] |= BRKIE;
1296 up->curregs[R15] |= BRKIE;
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1351 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1352 up->curregs[R3] = RxENAB | Rx8;
1353 up->curregs[R5] = TxENAB | Tx8;
1354 up->curregs[R6] = 0x00; /* SDLC Address */
1355 up->curregs[R7] = 0x7E; /* SDLC Flag */
1356 up->curregs[R9] = NV;
1357 up->curregs[R7p] = 0x00;
1361 up->curregs[R9] |= MIE;
1362 write_zsreg(channel, R9, up->curregs[R9]);
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1367 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1368 up->curregs[R3] = RxENAB | Rx8;
1369 up->curregs[R5] = TxENAB | Tx8;
1370 up->curregs[R6] = 0x00; /* SDLC Address */
1371 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R9] = NV;
1373 up->curregs[R10] = NRZ;
1374 up->curregs[R11] = TCBR | RCBR;
1377 up->curregs[R12] = (brg & 0xff);
1378 up->curregs[R13] = (brg >> 8) & 0xff;
1379 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1381 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1382 if (__load_zsregs(channel, up->curregs)) {
1387 up->curregs[R9] |= MIE;
1388 write_zsreg(channel, R9, up->curregs[R9]);
1597 up->curregs[R9] |= MIE;
1598 write_zsreg(channel, R9, up->curregs[R9]);
1634 up->curregs[R9] &= ~MIE;
1635 write_zsreg(channel, R9, up->curregs[R9]);