Lines Matching refs:up
113 struct uart_sc26xx_port *up;
117 up = container_of(port, struct uart_sc26xx_port, port[0]);
119 up->imr |= mask << (line * 4);
120 WRITE_SC(port, IMR, up->imr);
125 struct uart_sc26xx_port *up;
129 up = container_of(port, struct uart_sc26xx_port, port[0]);
131 up->imr &= ~(mask << (line * 4));
132 WRITE_SC(port, IMR, up->imr);
215 struct uart_sc26xx_port *up = dev_id;
220 spin_lock_irqsave(&up->port[0].lock, flags);
223 isr = READ_SC(&up->port[0], ISR);
225 transmit_chars(&up->port[0]);
227 tty = receive_chars(&up->port[0]);
229 spin_unlock(&up->port[0].lock);
234 spin_lock(&up->port[1].lock);
238 transmit_chars(&up->port[1]);
240 tty = receive_chars(&up->port[1]);
242 spin_unlock_irqrestore(&up->port[1].lock, flags);
259 struct uart_sc26xx_port *up;
263 up = container_of(port, struct uart_sc26xx_port, port[0]);
265 if (up->dtr_mask[line]) {
267 WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
269 WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
271 if (up->rts_mask[line]) {
273 WRITE_SC(port, OPR_SET, up->rts_mask[line]);
275 WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
282 struct uart_sc26xx_port *up;
288 up = container_of(port, struct uart_sc26xx_port, port[0]);
291 if (up->dsr_mask[line]) {
293 mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
295 if (up->cts_mask[line]) {
297 mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
299 if (up->dcd_mask[line]) {
301 mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
303 if (up->ri_mask[line]) {
305 mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
619 static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
622 up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
623 up->rts_mask[line] = sc26xx_flags2mask(data, 4);
624 up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
625 up->cts_mask[line] = sc26xx_flags2mask(data, 12);
626 up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
627 up->ri_mask[line] = sc26xx_flags2mask(data, 20);
633 struct uart_sc26xx_port *up;
641 up = kzalloc(sizeof *up, GFP_KERNEL);
642 if (unlikely(!up))
645 up->port[0].line = 0;
646 up->port[0].ops = &sc26xx_ops;
647 up->port[0].type = PORT_SC26XX;
648 up->port[0].uartclk = (29491200 / 16); /* arbitrary */
650 up->port[0].mapbase = res->start;
651 up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
652 up->port[0].iotype = UPIO_MEM;
653 up->port[0].irq = platform_get_irq(dev, 0);
655 up->port[0].dev = &dev->dev;
657 sc26xx_init_masks(up, 0, sc26xx_data[0]);
659 sc26xx_port = &up->port[0];
661 up->port[1].line = 1;
662 up->port[1].ops = &sc26xx_ops;
663 up->port[1].type = PORT_SC26XX;
664 up->port[1].uartclk = (29491200 / 16); /* arbitrary */
666 up->port[1].mapbase = up->port[0].mapbase;
667 up->port[1].membase = up->port[0].membase;
668 up->port[1].iotype = UPIO_MEM;
669 up->port[1].irq = up->port[0].irq;
671 up->port[1].dev = &dev->dev;
673 sc26xx_init_masks(up, 1, sc26xx_data[1]);
681 err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
685 err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
689 err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
693 dev_set_drvdata(&dev->dev, up);
697 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
699 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
705 kfree(up);
713 struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
715 free_irq(up->port[0].irq, up);
717 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
718 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
722 kfree(up);