Lines Matching refs:up
59 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
62 return readl(up->port.membase + offset);
65 static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
68 writel(value, up->port.membase + offset);
73 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
75 up->ier |= UART_IER_MSI;
76 serial_out(up, UART_IER, up->ier);
81 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
83 if (up->ier & UART_IER_THRI) {
84 up->ier &= ~UART_IER_THRI;
85 serial_out(up, UART_IER, up->ier);
91 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
93 up->ier &= ~UART_IER_RLSI;
94 up->port.read_status_mask &= ~UART_LSR_DR;
95 serial_out(up, UART_IER, up->ier);
98 static inline void receive_chars(struct uart_pxa_port *up, int *status)
100 struct tty_struct *tty = up->port.state->port.tty;
105 ch = serial_in(up, UART_RX);
107 up->port.icount.rx++;
116 up->port.icount.brk++;
123 if (uart_handle_break(&up->port))
126 up->port.icount.parity++;
128 up->port.icount.frame++;
130 up->port.icount.overrun++;
135 *status &= up->port.read_status_mask;
138 if (up->port.line == up->port.cons->index) {
140 *status |= up->lsr_break_flag;
141 up->lsr_break_flag = 0;
152 if (uart_handle_sysrq_char(&up->port, ch))
155 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
158 *status = serial_in(up, UART_LSR);
163 static void transmit_chars(struct uart_pxa_port *up)
165 struct circ_buf *xmit = &up->port.state->xmit;
168 if (up->port.x_char) {
169 serial_out(up, UART_TX, up->port.x_char);
170 up->port.icount.tx++;
171 up->port.x_char = 0;
174 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
175 serial_pxa_stop_tx(&up->port);
179 count = up->port.fifosize / 2;
181 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
183 up->port.icount.tx++;
189 uart_write_wakeup(&up->port);
193 serial_pxa_stop_tx(&up->port);
198 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
200 if (!(up->ier & UART_IER_THRI)) {
201 up->ier |= UART_IER_THRI;
202 serial_out(up, UART_IER, up->ier);
206 static inline void check_modem_status(struct uart_pxa_port *up)
210 status = serial_in(up, UART_MSR);
216 up->port.icount.rng++;
218 up->port.icount.dsr++;
220 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
222 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
224 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
232 struct uart_pxa_port *up = dev_id;
235 iir = serial_in(up, UART_IIR);
238 lsr = serial_in(up, UART_LSR);
240 receive_chars(up, &lsr);
241 check_modem_status(up);
243 transmit_chars(up);
249 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
253 spin_lock_irqsave(&up->port.lock, flags);
254 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
255 spin_unlock_irqrestore(&up->port.lock, flags);
262 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
266 status = serial_in(up, UART_MSR);
282 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
296 mcr |= up->mcr;
298 serial_out(up, UART_MCR, mcr);
303 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
306 spin_lock_irqsave(&up->port.lock, flags);
308 up->lcr |= UART_LCR_SBC;
310 up->lcr &= ~UART_LCR_SBC;
311 serial_out(up, UART_LCR, up->lcr);
312 spin_unlock_irqrestore(&up->port.lock, flags);
318 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
323 up->mcr |= UART_MCR_AFE;
325 up->mcr = 0;
327 up->port.uartclk = clk_get_rate(up->clk);
332 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
340 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
341 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
343 serial_out(up, UART_FCR, 0);
348 (void) serial_in(up, UART_LSR);
349 (void) serial_in(up, UART_RX);
350 (void) serial_in(up, UART_IIR);
351 (void) serial_in(up, UART_MSR);
356 serial_out(up, UART_LCR, UART_LCR_WLEN8);
358 spin_lock_irqsave(&up->port.lock, flags);
359 up->port.mctrl |= TIOCM_OUT2;
360 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
361 spin_unlock_irqrestore(&up->port.lock, flags);
368 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
369 serial_out(up, UART_IER, up->ier);
374 (void) serial_in(up, UART_LSR);
375 (void) serial_in(up, UART_RX);
376 (void) serial_in(up, UART_IIR);
377 (void) serial_in(up, UART_MSR);
384 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
387 free_irq(up->port.irq, up);
392 up->ier = 0;
393 serial_out(up, UART_IER, 0);
395 spin_lock_irqsave(&up->port.lock, flags);
396 up->port.mctrl &= ~TIOCM_OUT2;
397 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
398 spin_unlock_irqrestore(&up->port.lock, flags);
403 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
404 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
407 serial_out(up, UART_FCR, 0);
414 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
449 if ((up->port.uartclk / quot) < (2400 * 16))
451 else if ((up->port.uartclk / quot) < (230400 * 16))
460 spin_lock_irqsave(&up->port.lock, flags);
466 up->ier |= UART_IER_UUE;
473 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
475 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
477 up->port.read_status_mask |= UART_LSR_BI;
482 up->port.ignore_status_mask = 0;
484 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
486 up->port.ignore_status_mask |= UART_LSR_BI;
492 up->port.ignore_status_mask |= UART_LSR_OE;
499 up->port.ignore_status_mask |= UART_LSR_DR;
504 up->ier &= ~UART_IER_MSI;
505 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
506 up->ier |= UART_IER_MSI;
508 serial_out(up, UART_IER, up->ier);
511 up->mcr |= UART_MCR_AFE;
513 up->mcr &= ~UART_MCR_AFE;
515 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
516 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
518 dll = serial_in(up, UART_DLL);
521 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
522 serial_out(up, UART_LCR, cval); /* reset DLAB */
523 up->lcr = cval; /* Save LCR */
524 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
525 serial_out(up, UART_FCR, fcr);
526 spin_unlock_irqrestore(&up->port.lock, flags);
533 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
536 clk_enable(up->clk);
538 clk_disable(up->clk);
552 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
553 up->port.type = PORT_PXA;
566 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
567 return up->name;
580 static inline void wait_for_xmitr(struct uart_pxa_port *up)
584 /* Wait up to 10ms for the character(s) to be sent. */
586 status = serial_in(up, UART_LSR);
589 up->lsr_break_flag = UART_LSR_BI;
596 /* Wait up to 1s for flow control if necessary */
597 if (up->port.flags & UPF_CONS_FLOW) {
600 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
607 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
609 wait_for_xmitr(up);
610 serial_out(up, UART_TX, ch);
622 struct uart_pxa_port *up = serial_pxa_ports[co->index];
625 clk_enable(up->clk);
630 ier = serial_in(up, UART_IER);
631 serial_out(up, UART_IER, UART_IER_UUE);
633 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
639 wait_for_xmitr(up);
640 serial_out(up, UART_IER, ier);
642 clk_disable(up->clk);
648 struct uart_pxa_port *up;
656 up = serial_pxa_ports[co->index];
657 if (!up)
663 return uart_set_options(&up->port, co, baud, parity, bits, flow);