Lines Matching refs:write_zsreg
149 write_zsreg(uap, R1,
153 write_zsreg(uap, R4, regs[R4]);
156 write_zsreg(uap, R10, regs[R10]);
159 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
163 write_zsreg(uap, R15, regs[R15] | EN85C30);
164 write_zsreg(uap, R7, regs[R7P]);
167 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
170 write_zsreg(uap, R6, regs[R6]);
171 write_zsreg(uap, R7, regs[R7]);
174 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
177 write_zsreg(uap, R11, regs[R11]);
180 write_zsreg(uap, R12, regs[R12]);
181 write_zsreg(uap, R13, regs[R13]);
184 write_zsreg(uap, R14, regs[R14]);
187 write_zsreg(uap, R0, RES_EXT_INT);
188 write_zsreg(uap, R0, RES_EXT_INT);
191 write_zsreg(uap, R3, regs[R3]);
192 write_zsreg(uap, R5, regs[R5]);
195 write_zsreg(uap, R1, regs[R1]);
198 write_zsreg(uap, R9, regs[R9]);
238 write_zsreg(uap, R0, ERR_RES);
263 write_zsreg(uap, R0, ERR_RES);
345 write_zsreg(uap, R1, uap->curregs[R1]);
356 write_zsreg(uap, R0, RES_EXT_INT);
460 write_zsreg(uap, R0, RES_Tx_P);
485 write_zsreg(uap_a, R0, RES_H_IUS);
505 write_zsreg(uap_b, R0, RES_H_IUS);
596 write_zsreg(uap, R5, uap->curregs[R5]);
724 write_zsreg(uap, R15, uap->curregs[R15]);
758 write_zsreg(uap, R5, uap->curregs[R5]);
812 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
815 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
818 write_zsreg(uap, 4, X1CLK | MONSYNC);
819 write_zsreg(uap, 3, Rx8);
820 write_zsreg(uap, 5, Tx8 | RTS);
821 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
822 write_zsreg(uap, 11, RCBR | TCBR);
823 write_zsreg(uap, 12, 0);
824 write_zsreg(uap, 13, 0);
825 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
826 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
827 write_zsreg(uap, 3, Rx8 | RxENABLE);
828 write_zsreg(uap, 0, RES_EXT_INT);
829 write_zsreg(uap, 0, RES_EXT_INT);
830 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
837 write_zsreg(uap, 9, NV);
838 write_zsreg(uap, 4, X16CLK | SB_MASK);
839 write_zsreg(uap, 3, Rx8);
843 write_zsreg(uap, 0, RES_EXT_INT);
844 write_zsreg(uap, 0, ERR_RES);
868 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
871 write_zsreg(uap, 9, 0);
875 write_zsreg(uap, R1, 0);
876 write_zsreg(uap, R0, ERR_RES);
877 write_zsreg(uap, R0, ERR_RES);
878 write_zsreg(uap, R0, RES_H_IUS);
879 write_zsreg(uap, R0, RES_H_IUS);
900 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
901 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
912 write_zsreg(uap, R5, uap->curregs[R5]);
916 write_zsreg(uap, R5, uap->curregs[R5]);
979 write_zsreg(uap, R1, uap->curregs[R1]);
1012 write_zsreg(uap, R1, uap->curregs[R1]);
1217 write_zsreg(uap, R5, uap->curregs[R5]);
1267 write_zsreg(uap, R5, uap->curregs[R5]);
1330 write_zsreg(uap, R1, uap->curregs[R1]);
1340 write_zsreg(uap, R1, uap->curregs[R1]);
1720 write_zsreg(uap, R1, uap->curregs[R1]);
2096 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2097 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2102 write_zsreg(uap, R1, uap->curregs[1]);