Lines Matching refs:uap
38 * - maybe put something right into uap->clk_divisor
127 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
131 if (ZS_IS_ASLEEP(uap))
136 unsigned char stat = read_zsreg(uap, R1);
142 ZS_CLEARERR(uap);
143 zssync(uap);
144 ZS_CLEARFIFO(uap);
145 zssync(uap);
146 ZS_CLEARERR(uap);
149 write_zsreg(uap, R1,
153 write_zsreg(uap, R4, regs[R4]);
156 write_zsreg(uap, R10, regs[R10]);
159 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
163 write_zsreg(uap, R15, regs[R15] | EN85C30);
164 write_zsreg(uap, R7, regs[R7P]);
167 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
170 write_zsreg(uap, R6, regs[R6]);
171 write_zsreg(uap, R7, regs[R7]);
174 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
177 write_zsreg(uap, R11, regs[R11]);
180 write_zsreg(uap, R12, regs[R12]);
181 write_zsreg(uap, R13, regs[R13]);
184 write_zsreg(uap, R14, regs[R14]);
187 write_zsreg(uap, R0, RES_EXT_INT);
188 write_zsreg(uap, R0, RES_EXT_INT);
191 write_zsreg(uap, R3, regs[R3]);
192 write_zsreg(uap, R5, regs[R5]);
195 write_zsreg(uap, R1, regs[R1]);
198 write_zsreg(uap, R9, regs[R9]);
209 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
211 if (!ZS_REGS_HELD(uap)) {
212 if (ZS_TX_ACTIVE(uap)) {
213 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
216 pmz_load_zsregs(uap, uap->curregs);
221 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
231 if (!ZS_IS_OPEN(uap)) {
237 (void)read_zsreg(uap, R1);
238 write_zsreg(uap, R0, ERR_RES);
239 (void)read_zsdata(uap);
240 ch = read_zsreg(uap, R0);
248 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
250 (void)read_zsdata(uap);
253 tty = uap->port.state->port.tty;
259 r1 = read_zsreg(uap, R1);
260 ch = read_zsdata(uap);
263 write_zsreg(uap, R0, ERR_RES);
264 zssync(uap);
267 ch &= uap->parity_mask;
268 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
269 uap->flags &= ~PMACZILOG_FLAG_BREAK;
276 uap->port.sysrq = jiffies + HZ*5;
280 if (uap->port.sysrq) {
282 spin_unlock(&uap->port.lock);
283 swallow = uart_handle_sysrq_char(&uap->port, ch);
284 spin_lock(&uap->port.lock);
295 uap->port.icount.rx++;
302 uap->port.icount.brk++;
303 if (uart_handle_break(&uap->port))
307 uap->port.icount.parity++;
309 uap->port.icount.frame++;
311 uap->port.icount.overrun++;
312 r1 &= uap->port.read_status_mask;
321 if (uap->port.ignore_status_mask == 0xff ||
322 (r1 & uap->port.ignore_status_mask) == 0) {
337 ch = read_zsreg(uap, R0);
344 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
345 write_zsreg(uap, R1, uap->curregs[R1]);
346 zssync(uap);
351 static void pmz_status_handle(struct uart_pmac_port *uap)
355 status = read_zsreg(uap, R0);
356 write_zsreg(uap, R0, RES_EXT_INT);
357 zssync(uap);
359 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
361 uap->port.icount.dsr++;
368 if ((status ^ uap->prev_status) & DCD)
369 uart_handle_dcd_change(&uap->port,
371 if ((status ^ uap->prev_status) & CTS)
372 uart_handle_cts_change(&uap->port,
375 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
379 uap->flags |= PMACZILOG_FLAG_BREAK;
381 uap->prev_status = status;
384 static void pmz_transmit_chars(struct uart_pmac_port *uap)
388 if (ZS_IS_ASLEEP(uap))
390 if (ZS_IS_CONS(uap)) {
391 unsigned char status = read_zsreg(uap, R0);
405 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
407 if (ZS_REGS_HELD(uap)) {
408 pmz_load_zsregs(uap, uap->curregs);
409 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
412 if (ZS_TX_STOPPED(uap)) {
413 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
425 if (!ZS_IS_OPEN(uap))
428 if (uap->port.x_char) {
429 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
430 write_zsdata(uap, uap->port.x_char);
431 zssync(uap);
432 uap->port.icount.tx++;
433 uap->port.x_char = 0;
437 if (uap->port.state == NULL)
439 xmit = &uap->port.state->xmit;
441 uart_write_wakeup(&uap->port);
444 if (uart_tx_stopped(&uap->port))
447 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
448 write_zsdata(uap, xmit->buf[xmit->tail]);
449 zssync(uap);
452 uap->port.icount.tx++;
455 uart_write_wakeup(&uap->port);
460 write_zsreg(uap, R0, RES_Tx_P);
461 zssync(uap);
466 struct uart_pmac_port *uap = dev_id;
473 uap_a = pmz_get_port_A(uap);
529 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
534 spin_lock_irqsave(&uap->port.lock, flags);
535 status = read_zsreg(uap, R0);
536 spin_unlock_irqrestore(&uap->port.lock, flags);
547 struct uart_pmac_port *uap = to_pmz(port);
550 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
567 struct uart_pmac_port *uap = to_pmz(port);
571 if (ZS_IS_IRDA(uap))
574 if (ZS_IS_ASLEEP(uap) ||
575 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
580 if (ZS_IS_INTMODEM(uap)) {
592 uap->curregs[R5] |= set_bits;
593 uap->curregs[R5] &= ~clear_bits;
594 if (ZS_IS_ASLEEP(uap))
596 write_zsreg(uap, R5, uap->curregs[R5]);
598 set_bits, clear_bits, uap->curregs[R5]);
599 zssync(uap);
609 struct uart_pmac_port *uap = to_pmz(port);
613 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
616 status = read_zsreg(uap, R0);
645 struct uart_pmac_port *uap = to_pmz(port);
650 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
651 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
653 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
656 status = read_zsreg(uap, R0);
666 write_zsdata(uap, port->x_char);
667 zssync(uap);
673 write_zsdata(uap, xmit->buf[xmit->tail]);
674 zssync(uap);
679 uart_write_wakeup(&uap->port);
692 struct uart_pmac_port *uap = to_pmz(port);
694 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
700 uap->curregs[R1] &= ~RxINT_MASK;
701 pmz_maybe_update_regs(uap);
712 struct uart_pmac_port *uap = to_pmz(port);
715 if (ZS_IS_IRDA(uap) || uap->node == NULL)
717 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
718 if (new_reg != uap->curregs[R15]) {
719 uap->curregs[R15] = new_reg;
721 if (ZS_IS_ASLEEP(uap))
724 write_zsreg(uap, R15, uap->curregs[R15]);
734 struct uart_pmac_port *uap = to_pmz(port);
738 if (uap->node == NULL)
749 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
750 if (new_reg != uap->curregs[R5]) {
751 uap->curregs[R5] = new_reg;
754 if (ZS_IS_ASLEEP(uap)) {
758 write_zsreg(uap, R5, uap->curregs[R5]);
772 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
779 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
781 if (ZS_IS_INTMODEM(uap)) {
783 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
791 if (ZS_IS_INTMODEM(uap)) {
793 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
796 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
803 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
810 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
812 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
813 zssync(uap);
815 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
816 zssync(uap);
818 write_zsreg(uap, 4, X1CLK | MONSYNC);
819 write_zsreg(uap, 3, Rx8);
820 write_zsreg(uap, 5, Tx8 | RTS);
821 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
822 write_zsreg(uap, 11, RCBR | TCBR);
823 write_zsreg(uap, 12, 0);
824 write_zsreg(uap, 13, 0);
825 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
826 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
827 write_zsreg(uap, 3, Rx8 | RxENABLE);
828 write_zsreg(uap, 0, RES_EXT_INT);
829 write_zsreg(uap, 0, RES_EXT_INT);
830 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
837 write_zsreg(uap, 9, NV);
838 write_zsreg(uap, 4, X16CLK | SB_MASK);
839 write_zsreg(uap, 3, Rx8);
841 while (read_zsreg(uap, 0) & Rx_CH_AV) {
842 (void)read_zsreg(uap, 8);
843 write_zsreg(uap, 0, RES_EXT_INT);
844 write_zsreg(uap, 0, ERR_RES);
854 static int __pmz_startup(struct uart_pmac_port *uap)
858 memset(&uap->curregs, 0, sizeof(uap->curregs));
861 pwr_delay = pmz_set_scc_power(uap, 1);
864 pmz_fix_zero_bug_scc(uap);
867 uap->curregs[R9] = 0;
868 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
869 zssync(uap);
871 write_zsreg(uap, 9, 0);
872 zssync(uap);
875 write_zsreg(uap, R1, 0);
876 write_zsreg(uap, R0, ERR_RES);
877 write_zsreg(uap, R0, ERR_RES);
878 write_zsreg(uap, R0, RES_H_IUS);
879 write_zsreg(uap, R0, RES_H_IUS);
882 uap->curregs[R4] = X16CLK | SB1;
883 uap->curregs[R3] = Rx8;
884 uap->curregs[R5] = Tx8 | RTS;
885 if (!ZS_IS_IRDA(uap))
886 uap->curregs[R5] |= DTR;
887 uap->curregs[R12] = 0;
888 uap->curregs[R13] = 0;
889 uap->curregs[R14] = BRENAB;
892 uap->curregs[R15] = BRKIE;
895 uap->curregs[R9] |= NV | MIE;
897 pmz_load_zsregs(uap, uap->curregs);
900 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
901 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
904 uap->prev_status = read_zsreg(uap, R0);
909 static void pmz_irda_reset(struct uart_pmac_port *uap)
911 uap->curregs[R5] |= DTR;
912 write_zsreg(uap, R5, uap->curregs[R5]);
913 zssync(uap);
915 uap->curregs[R5] &= ~DTR;
916 write_zsreg(uap, R5, uap->curregs[R5]);
917 zssync(uap);
927 struct uart_pmac_port *uap = to_pmz(port);
933 if (ZS_IS_ASLEEP(uap))
935 if (uap->node == NULL)
940 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
945 if (!ZS_IS_CONS(uap)) {
947 pwr_delay = __pmz_startup(uap);
951 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
952 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
953 "SCC", uap)) {
955 pmz_set_scc_power(uap, 0);
971 if (ZS_IS_IRDA(uap))
972 pmz_irda_reset(uap);
976 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
977 if (!ZS_IS_EXTCLK(uap))
978 uap->curregs[R1] |= EXT_INT_ENAB;
979 write_zsreg(uap, R1, uap->curregs[R1]);
989 struct uart_pmac_port *uap = to_pmz(port);
994 if (uap->node == NULL)
1000 free_irq(uap->port.irq, uap);
1004 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1006 if (!ZS_IS_OPEN(uap->mate))
1007 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1010 if (!ZS_IS_ASLEEP(uap)) {
1011 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1012 write_zsreg(uap, R1, uap->curregs[R1]);
1013 zssync(uap);
1016 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1023 uap->curregs[R3] &= ~RxENABLE;
1024 uap->curregs[R5] &= ~TxENABLE;
1027 uap->curregs[R5] &= ~SND_BRK;
1028 pmz_maybe_update_regs(uap);
1031 pmz_set_scc_power(uap, 0);
1043 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1052 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1053 uap->curregs[R4] = X1CLK;
1054 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1055 uap->curregs[R14] = 0; /* BRG off */
1056 uap->curregs[R12] = 0;
1057 uap->curregs[R13] = 0;
1058 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1062 uap->curregs[R4] = X16CLK;
1063 uap->curregs[R11] = 0;
1064 uap->curregs[R14] = 0;
1067 uap->curregs[R4] = X32CLK;
1068 uap->curregs[R11] = 0;
1069 uap->curregs[R14] = 0;
1072 uap->curregs[R4] = X16CLK;
1073 uap->curregs[R11] = TCBR | RCBR;
1075 uap->curregs[R12] = (brg & 255);
1076 uap->curregs[R13] = ((brg >> 8) & 255);
1077 uap->curregs[R14] = BRENAB;
1079 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1083 uap->curregs[3] &= ~RxN_MASK;
1084 uap->curregs[5] &= ~TxN_MASK;
1088 uap->curregs[3] |= Rx5;
1089 uap->curregs[5] |= Tx5;
1090 uap->parity_mask = 0x1f;
1093 uap->curregs[3] |= Rx6;
1094 uap->curregs[5] |= Tx6;
1095 uap->parity_mask = 0x3f;
1098 uap->curregs[3] |= Rx7;
1099 uap->curregs[5] |= Tx7;
1100 uap->parity_mask = 0x7f;
1104 uap->curregs[3] |= Rx8;
1105 uap->curregs[5] |= Tx8;
1106 uap->parity_mask = 0xff;
1109 uap->curregs[4] &= ~(SB_MASK);
1111 uap->curregs[4] |= SB2;
1113 uap->curregs[4] |= SB1;
1115 uap->curregs[4] |= PAR_ENAB;
1117 uap->curregs[4] &= ~PAR_ENAB;
1119 uap->curregs[4] |= PAR_EVEN;
1121 uap->curregs[4] &= ~PAR_EVEN;
1123 uap->port.read_status_mask = Rx_OVR;
1125 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1127 uap->port.read_status_mask |= BRK_ABRT;
1129 uap->port.ignore_status_mask = 0;
1131 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1133 uap->port.ignore_status_mask |= BRK_ABRT;
1135 uap->port.ignore_status_mask |= Rx_OVR;
1139 uap->port.ignore_status_mask = 0xff;
1146 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1191 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1192 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1202 (void)read_zsdata(uap);
1203 (void)read_zsdata(uap);
1204 (void)read_zsdata(uap);
1206 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1207 read_zsdata(uap);
1216 uap->curregs[R5] |= DTR;
1217 write_zsreg(uap, R5, uap->curregs[R5]);
1218 zssync(uap);
1222 pmz_convert_to_zs(uap, CS8, 0, 19200);
1223 pmz_load_zsregs(uap, uap->curregs);
1227 write_zsdata(uap, 1);
1229 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1236 version = read_zsdata(uap);
1244 write_zsdata(uap, cmdbyte);
1246 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1253 t = read_zsdata(uap);
1260 (void)read_zsdata(uap);
1261 (void)read_zsdata(uap);
1262 (void)read_zsdata(uap);
1266 uap->curregs[R5] &= ~DTR;
1267 write_zsreg(uap, R5, uap->curregs[R5]);
1268 zssync(uap);
1270 (void)read_zsdata(uap);
1271 (void)read_zsdata(uap);
1272 (void)read_zsdata(uap);
1279 struct uart_pmac_port *uap = to_pmz(port);
1284 if (ZS_IS_ASLEEP(uap))
1287 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1289 if (ZS_IS_IRDA(uap)) {
1294 pmz_irda_setup(uap, &baud);
1296 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1297 pmz_load_zsregs(uap, uap->curregs);
1298 zssync(uap);
1301 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1303 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1304 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1305 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1307 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1308 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1312 pmz_maybe_update_regs(uap);
1323 struct uart_pmac_port *uap = to_pmz(port);
1329 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1330 write_zsreg(uap, R1, uap->curregs[R1]);
1336 if (ZS_IS_OPEN(uap)) {
1337 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1338 if (!ZS_IS_EXTCLK(uap))
1339 uap->curregs[R1] |= EXT_INT_ENAB;
1340 write_zsreg(uap, R1, uap->curregs[R1]);
1347 struct uart_pmac_port *uap = to_pmz(port);
1349 if (ZS_IS_IRDA(uap))
1351 else if (ZS_IS_INTMODEM(uap))
1383 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1385 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
1387 return read_zsdata(uap);
1392 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1395 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1397 write_zsdata(uap, c);
1432 static int __init pmz_init_port(struct uart_pmac_port *uap)
1434 struct device_node *np = uap->node;
1448 uap->port.mapbase = r_ports.start;
1449 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1451 uap->control_reg = uap->port.membase;
1452 uap->data_reg = uap->control_reg + 0x10;
1460 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1465 if (ZS_HAS_DMA(uap)) {
1466 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1467 if (uap->tx_dma_regs == NULL) {
1468 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1471 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1472 if (uap->rx_dma_regs == NULL) {
1473 iounmap(uap->tx_dma_regs);
1474 uap->tx_dma_regs = NULL;
1475 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1478 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1479 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1487 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1490 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1491 uap->port_type = PMAC_SCC_ASYNC;
1496 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1498 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1500 if (ZS_IS_IRDA(uap))
1501 uap->port_type = PMAC_SCC_IRDA;
1502 if (ZS_IS_INTMODEM(uap)) {
1515 uap->port_type = PMAC_SCC_I2S1;
1528 uap->port.iotype = UPIO_MEM;
1529 uap->port.irq = irq_of_parse_and_map(np, 0);
1530 uap->port.uartclk = ZS_CLOCK;
1531 uap->port.fifosize = 1;
1532 uap->port.ops = &pmz_pops;
1533 uap->port.type = PORT_PMAC_ZILOG;
1534 uap->port.flags = 0;
1542 if (uap->port.irq == NO_IRQ &&
1546 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1547 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1548 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1555 pmz_convert_to_zs(uap, CS8, 0, 9600);
1563 static void pmz_dispose_port(struct uart_pmac_port *uap)
1567 np = uap->node;
1568 iounmap(uap->rx_dma_regs);
1569 iounmap(uap->tx_dma_regs);
1570 iounmap(uap->control_reg);
1571 uap->node = NULL;
1573 memset(uap, 0, sizeof(struct uart_pmac_port));
1587 struct uart_pmac_port *uap = &pmz_ports[i];
1589 uap->dev = mdev;
1590 dev_set_drvdata(&mdev->ofdev.dev, uap);
1591 if (macio_request_resources(uap->dev, "pmac_zilog"))
1594 uap->node->name);
1596 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1608 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1610 if (!uap)
1613 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1614 macio_release_resources(uap->dev);
1615 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1618 uap->dev = NULL;
1626 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1630 if (uap == NULL) {
1631 printk("HRM... pmz_suspend with NULL uap\n");
1640 state = pmz_uart_reg.state + uap->port.line;
1645 spin_lock_irqsave(&uap->port.lock, flags);
1647 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1649 uap->curregs[R3] &= ~RxENABLE;
1650 uap->curregs[R5] &= ~TxENABLE;
1653 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1654 uap->curregs[R5] &= ~SND_BRK;
1655 pmz_load_zsregs(uap, uap->curregs);
1656 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1660 spin_unlock_irqrestore(&uap->port.lock, flags);
1662 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1663 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1664 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1665 disable_irq(uap->port.irq);
1668 if (ZS_IS_CONS(uap))
1669 uap->port.cons->flags &= ~CON_ENABLED;
1672 pmz_set_scc_power(uap, 0);
1687 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1692 if (uap == NULL)
1700 state = pmz_uart_reg.state + uap->port.line;
1705 spin_lock_irqsave(&uap->port.lock, flags);
1706 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1707 spin_unlock_irqrestore(&uap->port.lock, flags);
1710 pwr_delay = __pmz_startup(uap);
1713 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1715 if (ZS_IS_OPEN(uap)) {
1717 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1718 if (!ZS_IS_EXTCLK(uap))
1719 uap->curregs[R1] |= EXT_INT_ENAB;
1720 write_zsreg(uap, R1, uap->curregs[R1]);
1723 spin_unlock_irqrestore(&uap->port.lock, flags);
1725 if (ZS_IS_CONS(uap))
1726 uap->port.cons->flags |= CON_ENABLED;
1729 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1730 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1731 enable_irq(uap->port.irq);
1827 static int __init pmz_init_port(struct uart_pmac_port *uap)
1832 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
1833 irq = platform_get_irq(uap->node, 0);
1837 uap->port.mapbase = r_ports->start;
1838 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1839 uap->port.iotype = UPIO_MEM;
1840 uap->port.irq = irq;
1841 uap->port.uartclk = ZS_CLOCK;
1842 uap->port.fifosize = 1;
1843 uap->port.ops = &pmz_pops;
1844 uap->port.type = PORT_PMAC_ZILOG;
1845 uap->port.flags = 0;
1847 uap->control_reg = uap->port.membase;
1848 uap->data_reg = uap->control_reg + 4;
1849 uap->port_type = 0;
1851 pmz_convert_to_zs(uap, CS8, 0, 9600);
1883 static void pmz_dispose_port(struct uart_pmac_port *uap)
1885 memset(uap, 0, sizeof(struct uart_pmac_port));
2074 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
2077 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
2079 write_zsdata(uap, ch);
2088 struct uart_pmac_port *uap = &pmz_ports[con->index];
2091 if (ZS_IS_ASLEEP(uap))
2093 spin_lock_irqsave(&uap->port.lock, flags);
2096 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2097 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2099 uart_console_write(&uap->port, s, count, pmz_console_putchar);
2102 write_zsreg(uap, R1, uap->curregs[1]);
2105 spin_unlock_irqrestore(&uap->port.lock, flags);
2113 struct uart_pmac_port *uap;
2136 uap = &pmz_ports[co->index];
2137 if (uap->node == NULL)
2139 port = &uap->port;
2144 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2154 pwr_delay = __pmz_startup(uap);