Lines Matching refs:curregs
216 pmz_load_zsregs(uap, uap->curregs);
344 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
345 write_zsreg(uap, R1, uap->curregs[R1]);
408 pmz_load_zsregs(uap, uap->curregs);
592 uap->curregs[R5] |= set_bits;
593 uap->curregs[R5] &= ~clear_bits;
596 write_zsreg(uap, R5, uap->curregs[R5]);
598 set_bits, clear_bits, uap->curregs[R5]);
700 uap->curregs[R1] &= ~RxINT_MASK;
717 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
718 if (new_reg != uap->curregs[R15]) {
719 uap->curregs[R15] = new_reg;
724 write_zsreg(uap, R15, uap->curregs[R15]);
749 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
750 if (new_reg != uap->curregs[R5]) {
751 uap->curregs[R5] = new_reg;
758 write_zsreg(uap, R5, uap->curregs[R5]);
858 memset(&uap->curregs, 0, sizeof(uap->curregs));
867 uap->curregs[R9] = 0;
882 uap->curregs[R4] = X16CLK | SB1;
883 uap->curregs[R3] = Rx8;
884 uap->curregs[R5] = Tx8 | RTS;
886 uap->curregs[R5] |= DTR;
887 uap->curregs[R12] = 0;
888 uap->curregs[R13] = 0;
889 uap->curregs[R14] = BRENAB;
892 uap->curregs[R15] = BRKIE;
895 uap->curregs[R9] |= NV | MIE;
897 pmz_load_zsregs(uap, uap->curregs);
900 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
901 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
911 uap->curregs[R5] |= DTR;
912 write_zsreg(uap, R5, uap->curregs[R5]);
915 uap->curregs[R5] &= ~DTR;
916 write_zsreg(uap, R5, uap->curregs[R5]);
976 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
978 uap->curregs[R1] |= EXT_INT_ENAB;
979 write_zsreg(uap, R1, uap->curregs[R1]);
1011 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1012 write_zsreg(uap, R1, uap->curregs[R1]);
1023 uap->curregs[R3] &= ~RxENABLE;
1024 uap->curregs[R5] &= ~TxENABLE;
1027 uap->curregs[R5] &= ~SND_BRK;
1053 uap->curregs[R4] = X1CLK;
1054 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1055 uap->curregs[R14] = 0; /* BRG off */
1056 uap->curregs[R12] = 0;
1057 uap->curregs[R13] = 0;
1062 uap->curregs[R4] = X16CLK;
1063 uap->curregs[R11] = 0;
1064 uap->curregs[R14] = 0;
1067 uap->curregs[R4] = X32CLK;
1068 uap->curregs[R11] = 0;
1069 uap->curregs[R14] = 0;
1072 uap->curregs[R4] = X16CLK;
1073 uap->curregs[R11] = TCBR | RCBR;
1075 uap->curregs[R12] = (brg & 255);
1076 uap->curregs[R13] = ((brg >> 8) & 255);
1077 uap->curregs[R14] = BRENAB;
1083 uap->curregs[3] &= ~RxN_MASK;
1084 uap->curregs[5] &= ~TxN_MASK;
1088 uap->curregs[3] |= Rx5;
1089 uap->curregs[5] |= Tx5;
1093 uap->curregs[3] |= Rx6;
1094 uap->curregs[5] |= Tx6;
1098 uap->curregs[3] |= Rx7;
1099 uap->curregs[5] |= Tx7;
1104 uap->curregs[3] |= Rx8;
1105 uap->curregs[5] |= Tx8;
1109 uap->curregs[4] &= ~(SB_MASK);
1111 uap->curregs[4] |= SB2;
1113 uap->curregs[4] |= SB1;
1115 uap->curregs[4] |= PAR_ENAB;
1117 uap->curregs[4] &= ~PAR_ENAB;
1119 uap->curregs[4] |= PAR_EVEN;
1121 uap->curregs[4] &= ~PAR_EVEN;
1216 uap->curregs[R5] |= DTR;
1217 write_zsreg(uap, R5, uap->curregs[R5]);
1223 pmz_load_zsregs(uap, uap->curregs);
1266 uap->curregs[R5] &= ~DTR;
1267 write_zsreg(uap, R5, uap->curregs[R5]);
1297 pmz_load_zsregs(uap, uap->curregs);
1304 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1307 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1329 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1330 write_zsreg(uap, R1, uap->curregs[R1]);
1337 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1339 uap->curregs[R1] |= EXT_INT_ENAB;
1340 write_zsreg(uap, R1, uap->curregs[R1]);
1649 uap->curregs[R3] &= ~RxENABLE;
1650 uap->curregs[R5] &= ~TxENABLE;
1653 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1654 uap->curregs[R5] &= ~SND_BRK;
1655 pmz_load_zsregs(uap, uap->curregs);
1717 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1719 uap->curregs[R1] |= EXT_INT_ENAB;
1720 write_zsreg(uap, R1, uap->curregs[R1]);
2096 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2097 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2102 write_zsreg(uap, R1, uap->curregs[1]);