Lines Matching refs:msm_write
49 msm_write(port, msm_port->imr, UART_IMR);
57 msm_write(port, msm_port->imr, UART_IMR);
65 msm_write(port, msm_port->imr, UART_IMR);
73 msm_write(port, msm_port->imr, UART_IMR);
88 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
131 msm_write(port, port->x_char, UART_TF);
140 msm_write(port, msm_port->imr, UART_IMR);
144 msm_write(port, xmit->buf[xmit->tail], UART_TF);
157 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
170 msm_write(port, 0, UART_IMR); /* disable interrupt */
179 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
203 msm_write(port, mr, UART_MR1);
204 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
207 msm_write(port, mr, UART_MR1);
214 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
216 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
276 msm_write(port, baud_code, UART_CSR);
282 msm_write(port, watermark, UART_IPR);
286 msm_write(port, watermark, UART_RFWR);
289 msm_write(port, 10, UART_TFWR);
297 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
298 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
299 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
300 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
301 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
302 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
340 msm_write(port, data, UART_MR1);
347 msm_write(port, data, UART_IPR);
352 msm_write(port, 0x05, UART_CR); /* enable TX & RX */
357 msm_write(port, msm_port->imr, UART_IMR);
367 msm_write(port, 0, UART_IMR); /* disable interrupts */
426 msm_write(port, mr, UART_MR2);
435 msm_write(port, mr, UART_MR1);
590 msm_write(port, c, UART_TF);
632 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,