Lines Matching refs:UCR1
59 #define UCR1 0x80 /* Control Register 1 */
277 temp = readl(sport->port.membase + UCR1);
279 writel(temp, sport->port.membase + UCR1);
289 temp = readl(sport->port.membase + UCR1);
291 writel(temp, sport->port.membase + UCR1);
300 temp = readl(sport->port.membase + UCR1);
301 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
361 temp = readl(sport->port.membase + UCR1);
363 writel(temp, sport->port.membase + UCR1);
366 temp = readl(sport->port.membase + UCR1);
367 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
370 temp = readl(sport->port.membase + UCR1);
372 writel(temp, sport->port.membase + UCR1);
501 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
560 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
565 writel(temp, sport->port.membase + UCR1);
671 temp = readl(sport->port.membase + UCR1);
679 writel(temp, sport->port.membase + UCR1);
781 temp = readl(sport->port.membase + UCR1);
786 writel(temp, sport->port.membase + UCR1);
882 old_ucr1 = readl(sport->port.membase + UCR1);
884 sport->port.membase + UCR1);
932 writel(old_ucr1, sport->port.membase + UCR1);
1063 * First, save UCR1/2 and then disable interrupts
1065 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1073 writel(ucr1, sport->port.membase + UCR1);
1081 * and restore UCR1/2
1085 writel(old_ucr1, sport->port.membase + UCR1);
1098 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {