Lines Matching refs:DC390_write8
532 DC390_write8 (Scsi_Dest_ID, pDCB->TargetID);
533 DC390_write8 (Sync_Period, pDCB->SyncPeriod);
534 DC390_write8 (Sync_Offset, pDCB->SyncOffset);
535 DC390_write8 (CtrlReg1, pDCB->CtrlR1);
536 DC390_write8 (CtrlReg3, pDCB->CtrlR3);
537 DC390_write8 (CtrlReg4, pDCB->CtrlR4);
538 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD); /* Flush FIFO */
561 DC390_write8 (ScsiFifo, IDENTIFY(disc_allowed, pDCB->TargetLUN));
564 DC390_write8(ScsiFifo, tag[0]);
567 DC390_write8(ScsiFifo, tag[1]);
599 DC390_write8 (ScsiFifo, REQUEST_SENSE);
600 DC390_write8 (ScsiFifo, pDCB->TargetLUN << 5);
601 DC390_write8 (ScsiFifo, 0);
602 DC390_write8 (ScsiFifo, 0);
603 DC390_write8 (ScsiFifo, SCSI_SENSE_BUFFERSIZE);
604 DC390_write8 (ScsiFifo, 0);
612 DC390_write8 (ScsiFifo, *(ptr++));
619 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
626 //DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
630 DC390_write8 (ScsiCmd, cmd);
643 DC390_write8(ScsiCmd, CLEAR_FIFO_CMD);
806 DC390_write8 (DMA_Cmd, WRITE_DIRECTION+DMA_IDLE_CMD);
807 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
849 DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD);
887 DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_BLAST_CMD);
896 //DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD);
933 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
934 DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD);
953 DC390_write8 (ScsiCmd, MSG_ACCEPTED_CMD);
961 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
968 DC390_write8 (Sync_Period, pDCB->SyncPeriod);
969 DC390_write8 (Sync_Offset, pDCB->SyncOffset);
970 DC390_write8 (CtrlReg3, pDCB->CtrlR3);
971 DC390_write8 (CtrlReg4, pDCB->CtrlR4);
988 #define DC390_ENABLE_MSGOUT DC390_write8 (ScsiCmd, SET_ATN_CMD)
1232 DC390_write8 (ScsiCmd, RESET_ATN_CMD);
1274 DC390_write8 (ScsiCmd, MSG_ACCEPTED_CMD);
1275 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
1307 DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir);
1316 DC390_write8 (CtcReg_Low, (u8) lval);
1318 DC390_write8 (CtcReg_Mid, (u8) lval);
1320 DC390_write8 (CtcReg_High, (u8) lval);
1325 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir);
1328 DC390_write8 (ScsiCmd, DMA_COMMAND+INFO_XFER_CMD);
1330 DC390_write8 (DMA_Cmd, DMA_START_CMD | ioDir);
1344 DC390_write8 (CtcReg_Low, 0);
1345 DC390_write8 (CtcReg_Mid, 0);
1346 DC390_write8 (CtcReg_High, 0);
1349 DC390_write8 (ScsiCmd, DMA_COMMAND+XFER_PAD_BYTE);
1351 DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir);
1352 DC390_write8 (DMA_Cmd, DMA_START_CMD | ioDir);
1377 DC390_write8 (ScsiCmd, RESET_ATN_CMD);
1378 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
1384 DC390_write8 (ScsiFifo, *(ptr++));
1388 DC390_write8 (ScsiFifo, REQUEST_SENSE);
1390 DC390_write8 (ScsiFifo, pDCB->TargetLUN << 5);
1391 DC390_write8 (ScsiFifo, 0);
1392 DC390_write8 (ScsiFifo, 0);
1393 DC390_write8 (ScsiFifo, SCSI_SENSE_BUFFERSIZE);
1394 DC390_write8 (ScsiFifo, 0);
1398 DC390_write8 (ScsiCmd, INFO_XFER_CMD);
1404 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
1406 DC390_write8 (ScsiCmd, INITIATOR_CMD_CMPLTE);
1407 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
1417 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
1426 DC390_write8 (ScsiFifo, *(ptr++));
1442 DC390_write8 (ScsiFifo, bval);
1444 DC390_write8 (ScsiCmd, INFO_XFER_CMD);
1450 DC390_write8 (ScsiFifo, EXTENDED_MESSAGE);
1451 DC390_write8 (ScsiFifo, 3); /* ;length of extended msg */
1452 DC390_write8 (ScsiFifo, EXTENDED_SDTR); /* ; sync nego */
1453 DC390_write8 (ScsiFifo, pDCB->NegoPeriod);
1455 DC390_write8 (ScsiFifo, pDCB->SyncOffset);
1457 DC390_write8 (ScsiFifo, SYNC_NEGO_OFFSET);
1459 DC390_write8 (ScsiCmd, INFO_XFER_CMD);
1466 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
1472 DC390_write8 (ScsiCmd, INFO_XFER_CMD);
1473 //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
1536 DC390_write8 (ScsiCmd, EN_SEL_RESEL);
1539 DC390_write8 (ScsiCmd, EN_SEL_RESEL);
1662 DC390_write8 (Scsi_Dest_ID, pDCB->TargetID);
1663 DC390_write8 (Sync_Period, pDCB->SyncPeriod);
1664 DC390_write8 (Sync_Offset, pDCB->SyncOffset);
1665 DC390_write8 (CtrlReg1, pDCB->CtrlR1);
1666 DC390_write8 (CtrlReg3, pDCB->CtrlR3);
1667 DC390_write8 (CtrlReg4, pDCB->CtrlR4); /* ; Glitch eater */
1668 DC390_write8 (ScsiCmd, MSG_ACCEPTED_CMD); /* ;to release the /ACK signal */
1844 //DC390_write8 (ScsiCmd, RST_DEVICE_CMD);
1846 //DC390_write8 (ScsiCmd, NOP_CMD);
1848 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
1849 DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
1850 DC390_write8 (ScsiCmd, RST_SCSI_BUS_CMD);
1862 DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
1866 DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
2044 DC390_write8(CtrlReg1, bval); /* disable IRQ on bus reset */
2054 DC390_write8(ScsiCmd, CLEAR_FIFO_CMD);
2063 DC390_write8(CtrlReg1, bval); /* re-enable interrupt */
2377 DC390_write8(CtrlReg1, DIS_INT_ON_SCSI_RST | shost->this_id);
2392 DC390_write8(Scsi_TimeOut, SEL_TIMEOUT);
2395 DC390_write8(Clk_Factor, CLK_FREQ_40MHZ);
2398 DC390_write8(ScsiCmd, NOP_CMD);
2401 DC390_write8(CtrlReg2, EN_FEATURE+EN_SCSI2_CMD);
2404 DC390_write8(CtrlReg3, FAST_CLK);
2407 DC390_write8(CtrlReg4, pACB->glitch_cfg | /* glitch eater */
2412 DC390_write8(CtcReg_High, 0);
2413 DC390_write8(DMA_Cmd, DMA_IDLE_CMD);
2414 DC390_write8(ScsiCmd, CLEAR_FIFO_CMD);
2418 DC390_write8(DMA_Status, dstate);
2543 DC390_write8 (CtrlReg1, bval); /* disable interrupt */