Lines Matching refs:dregs
100 static volatile struct sun3_dma_regs *dregs;
188 dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);
190 if(sun3_map_test((unsigned long)dregs, &x)) {
193 oldcsr = dregs->csr;
194 dregs->csr = 0;
196 if(dregs->csr == 0x1400)
199 dregs->csr = oldcsr;
254 dregs->csr = 0;
256 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
258 dregs->fifo_count = 0;
259 dregs->fifo_count_hi = 0;
260 dregs->dma_addr_hi = 0;
261 dregs->dma_addr_lo = 0;
262 dregs->dma_count_hi = 0;
263 dregs->dma_count_lo = 0;
265 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
341 unsigned short csr = dregs->csr;
344 dregs->csr &= ~CSR_DMA_ENABLE;
356 dregs->fifo_count,
357 dregs->dma_count_lo | (dregs->dma_count_hi << 16),
359 dregs->dma_addr_lo | (dregs->dma_addr_hi << 16));
403 // dregs->fifo_count = 0;
406 dregs->csr |= CSR_SEND;
408 dregs->csr &= ~CSR_SEND;
411 // dregs->csr &= ~CSR_FIFO;
412 // dregs->csr |= CSR_FIFO;
414 dregs->csr |= CSR_PACK_ENABLE;
416 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
417 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
419 dregs->dma_count_hi = 0;
420 dregs->dma_count_lo = 0;
421 dregs->fifo_count_hi = 0;
422 dregs->fifo_count = 0;
425 printk("scsi: dma_setup done csr %x\n", dregs->csr);
451 csr = dregs->csr;
453 printk("scsi: dma_start data %p count %x csr %x fifo %x\n", data, count, csr, dregs->fifo_count);
456 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
457 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
459 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
460 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
463 // dregs->csr |= CSR_DMA_ENABLE;
476 dregs->csr &= ~CSR_DMA_ENABLE;
478 fifo = dregs->fifo_count;
489 if((!write_flag) && (dregs->csr & CSR_LEFT)) {
501 switch(dregs->csr & CSR_LEFT) {
503 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
507 *vaddr = (dregs->bpack_hi & 0x00ff);
511 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
521 dregs->dma_addr_hi = 0;
522 dregs->dma_addr_lo = 0;
523 dregs->dma_count_hi = 0;
524 dregs->dma_count_lo = 0;
526 dregs->fifo_count = 0;
527 dregs->fifo_count_hi = 0;
529 dregs->csr &= ~CSR_SEND;
531 // dregs->csr |= CSR_DMA_ENABLE;