Lines Matching refs:NCR5380_write
119 * NCR5380_write(register, value) - write to the specific register
776 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
777 NCR5380_write(MODE_REG, MR_BASE);
778 NCR5380_write(TARGET_COMMAND_REG, 0);
779 NCR5380_write(SELECT_ENABLE_REG, 0);
1118 NCR5380_write(MODE_REG, MR_BASE);
1119 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1313 NCR5380_write(TARGET_COMMAND_REG, 0);
1320 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1321 NCR5380_write(MODE_REG, MR_ARBITRATE);
1336 NCR5380_write(MODE_REG, MR_BASE);
1337 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1349 NCR5380_write(MODE_REG, MR_BASE);
1366 NCR5380_write(MODE_REG, MR_BASE);
1375 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_SEL |
1380 NCR5380_write(MODE_REG, MR_BASE);
1381 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1400 NCR5380_write(MODE_REG, MR_BASE);
1401 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1412 NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << cmd->device->id)));
1420 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY |
1422 NCR5380_write(MODE_REG, MR_BASE);
1430 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1434 NCR5380_write(SELECT_ENABLE_REG, 0);
1443 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA |
1485 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1488 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1494 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1505 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1507 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1572 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1592 NCR5380_write(OUTPUT_DATA_REG, *d);
1607 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1610 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1613 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1616 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1621 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
1641 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1643 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1681 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1695 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1698 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1701 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1766 NCR5380_write(TARGET_COMMAND_REG, 1);
1768 NCR5380_write(INITIATOR_COMMAND_REG, 0);
1769 NCR5380_write(MODE_REG, (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR));
1770 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);
1772 NCR5380_write(TARGET_COMMAND_REG, 0);
1774 NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_DATA);
1775 NCR5380_write(MODE_REG, (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR));
1776 NCR5380_write(START_DMA_SEND_REG, 0);
1849 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1851 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1854 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1923 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1956 NCR5380_write(SELECT_ENABLE_REG, 0); /* disable reselects */
1975 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1981 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2015 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2042 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2098 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2103 NCR5380_write(TARGET_COMMAND_REG, 0);
2111 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2113 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2136 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2152 NCR5380_write(TARGET_COMMAND_REG, 0);
2155 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2176 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2178 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2195 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2209 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2259 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
2281 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2337 NCR5380_write(MODE_REG, MR_BASE);
2353 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);
2356 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2365 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));
2442 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
2444 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2454 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
2504 /* NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_ATN); */
2672 NCR5380_write( TARGET_COMMAND_REG,
2675 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
2678 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
2679 NCR5380_write( MODE_REG, MR_BASE );
2680 NCR5380_write( TARGET_COMMAND_REG, 0 );
2681 NCR5380_write( SELECT_ENABLE_REG, 0 );