Lines Matching refs:ctrl_status
906 uint32_t ctrl_status;
920 ctrl_status = readw(&ha->reg->ctrl_status);
921 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0)
922 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
925 writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);
926 readl(&ha->reg->ctrl_status);
941 uint32_t ctrl_status;
949 ctrl_status = readw(&ha->reg->ctrl_status);
952 if ((ctrl_status & CSR_NET_RESET_INTR) == 0)
958 if ((ctrl_status & CSR_NET_RESET_INTR) != 0) {
964 writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status);
965 readl(&ha->reg->ctrl_status);
973 ctrl_status = readw(&ha->reg->ctrl_status);
976 if ((ctrl_status & CSR_SOFT_RESET) == 0) {
989 ctrl_status = readw(&ha->reg->ctrl_status);
990 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0) {
991 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
992 readl(&ha->reg->ctrl_status);
999 writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status);
1000 readl(&ha->reg->ctrl_status);
1006 ctrl_status = readw(&ha->reg->ctrl_status);
1009 if ((ctrl_status & CSR_FORCE_SOFT_RESET) == 0) {
1282 while ((readw(&ha->reg->ctrl_status) &