Lines Matching refs:mem_crb
1175 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1182 mem_crb = QLA82XX_CRB_QDR_NET;
1184 mem_crb = QLA82XX_CRB_DDR_NET;
1202 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1204 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1206 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1208 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1211 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1227 mem_crb + MIU_TEST_AGT_RDDATA(k));
1266 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1272 mem_crb = QLA82XX_CRB_QDR_NET;
1274 mem_crb = QLA82XX_CRB_DDR_NET;
1327 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1329 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1331 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1333 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1335 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1338 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1342 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1344 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1347 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);