scsi/qla2xxx/qla_init.c

652 		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
654 			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
675 		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
677 			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
842 		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
845 				if ((RD_REG_WORD(&reg->hccr) &
851 			RD_REG_WORD(&reg->hccr);	/* PCI Posting. */
893 		WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
894 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */
897 		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
898 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */
901 	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
902 	WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
925 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
930 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
931 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */
949 		WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
950 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */
1003 	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1004 	RD_REG_DWORD(&reg->hccr);
1006 	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1007 	RD_REG_DWORD(&reg->hccr);
1009 	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1010 	RD_REG_DWORD(&reg->hccr);
1095 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1096 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1424 		WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1425 		RD_REG_WORD(&reg->hccr);
1488 			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1491 			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1492 		RD_REG_WORD(&reg->hccr);
1738 	RD_REG_DWORD(&ioreg->hccr);
4168 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4169 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */
4170 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4171 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */
4189 	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4190 	RD_REG_DWORD(&reg->hccr);
4191 	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4192 	RD_REG_DWORD(&reg->hccr);